MCF5329CVM240J Freescale Semiconductor, MCF5329CVM240J Datasheet - Page 30
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MCF5329CVM240J
Manufacturer Part Number
MCF5329CVM240J
Description
IC MPU RISC 240MHZ 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF532xr
Datasheet
1.MCF5328CVM240J.pdf
(50 pages)
Specifications of MCF5329CVM240J
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
240MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, SSI, UART/USART, USB, USB OTG
Peripherals
DMA, LCD, PWM, WDT
Number Of I /o
94
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Family Name
MPC5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
240MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.6/1.95/2.75/3.6V
Operating Supply Voltage (min)
1.4/1.7/2.25/3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Processor Series
MCF532xx
Core
ColdFire V3
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5329CVM240J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Electrical Characteristics
5.10
This sections lists the timing specifications for the LCD Controller.
30
LCD_LD[17:0]
LCD_LD[15:0]
LCD_HSYNC
LCD_HSYNC
LCD_VSYNC
LCD_LSCLK
Note: The pixel clock is equal to LCD_LSCLK / (PCD + 1). When it is in CSTN, TFT or monochrome mode with
LCD_OE
LCD_OE
LCD Controller Timing Specifications
Num
T1
T2
T3
bus width is set and LCD_LSCLK is equal to the pixel clock. When it is in monochrome with other bus
width settings, LCD_LSCLK is equal to the pixel clock divided by bus width. The polarity of LCD_LSCLK
and LCD_LD signals can also be programmed.
T2
Figure 16. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Line Y
LCD_LD[17:0]
LCD_LSCLK
Figure 15. LCD_LSCLK to LCD_LD[17:0] timing diagram
T5
MCF532x ColdFire
T1
Pixel data setup time
LCD_LSCLK Period
Pixel data up time
Non-display region
T6
Table 14. LCD_LSCLK Timing
Parameter
T3
®
Microprocessor Data Sheet, Rev. 5
(1,1)
T2
(1,2)
XMAX
T4
T3
T1
(1,X)
Minimum
Line 1
25
11
11
T7
Display region
Maximum
2000
—
—
Line Y
Freescale Semiconductor
Unit
ns
ns
ns