MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 21

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
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Num
All values given are initial design targets and subject to change.
All internal registers retain data at 0 Hz.
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL
into self clocked mode.
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls
below f
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
This specification applies to the period required for the PLL to relock after changing the MFD frequency
control bits in the synthesizer control register (SYNCR).
Assuming a reference is available at power up, lock time is measured from the time V
valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the
crystal start up time must be added to the PLL lock time to determine the total start-up time.
2).
PLL is operating in 1:1 PLL mode.
Jitter is the average deviation from the programmed frequency measured over the specified interval at
maximum f
stable external clock signal. Noise injected into the PLL circuitry via V
crystal oscillator frequency increase the Cjitter percentage for a given interval.
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of
Cjitter+Cmod.
Modulation percentage applies over an interval of 10μs, or equivalently the modulation rate is 100KHz.
Modulation rate selected must not result in f
Modulation range determined by hardware design.
f
10
11
12
13
14
15
t
sys/2
6
7
8
9
lpll
= (64
= f
LOR
XTAL Load Capacitance
PLL Lock Time
Power-up To Lock Time
With Crystal Reference (includes 5 time)
Without Crystal Reference
1:1 Mode Clock Skew (between CLKOUT
and EXTAL)
Duty Cycle of reference
Frequency un-LOCK Range
Frequency LOCK Range
CLKOUT Period Jitter,
Measured at f
edge)
interval)
Frequency Modulation Range Limit
(f
ICO Frequency. f
ico
sys/2
Peak-to-peak Jitter (Clock edge to clock
Long Term Jitter (Averaged over 2 ms
*
/ (2
sys/2
4
with default MFD/RFD settings.
*
Table 10. HiP7 PLLMRFM Electrical Specifications
Max must not be exceeded)
5 + 5 τ) T
*
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4
. Measurements are made with the device powered by filtered supplies and clocked by a
2
RFD
10
Characteristic
)
sys/2
5, 7,13
ico
ref
Max
, where T
= f
ref
5, 6, 8,11, 12
5
5
5, 6,8
× 2 × (MFD+2)
9
ref
= 1/F
13,14
sys/2
ref_crystal
15
value greater than the f
= 1/F
Symbol
C
C
t
f
t
skew
f
LCK
f
t
t
lplk
UL
jitter
mod
ico
lpll
dc
ref_ext
= 1/F
DDSYN
ref_1:1
Value
Min.
–1.7
–3.8
0.8
—
—
—
–1
40
—
—
48
sys/2
5
1
(continued)
, and τ = 1.57x10
and V
maximum specified value.
SSSYN
Value
Max.
750
750
150
DD
4.1
2.0
5.0
.01
2.2
30
11
60
1
Electrical Characteristics
and V
and variation in
-6
DDSYN
2(MFD +
% f
% f
% f
%f
MHz
Unit
ms
pF
μs
μs
ns
%
sys/2
sys/2
sys/2
sys/2
are
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