R5F2L387ANFP#U1 Renesas Electronics America, R5F2L387ANFP#U1 Datasheet - Page 251
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R5F2L387ANFP#U1
Manufacturer Part Number
R5F2L387ANFP#U1
Description
MCU 1KB FLASH 48K ROM 80-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/38Ar
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L387ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
68
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Company
Part Number
Manufacturer
Quantity
Price
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R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 214 of 802
Figure 15.11
Figure 15.12
15.3.8
Table 15.8
j = 0 to 23
X: 0 or 1
CPU clock
Address
Bits b3 to b0
in DTCCR
Register
00X0b
01X0b
10X0b
X001b
X101b
11X0b
0X11b
1X11b
The DTC requires five clock cycles to read control data allocated in the DTC control data area. The number of
clock cycles required to write back control data differs depending on the control data settings.
Figure 15.11 shows an Example of DTC Operation Timings and Figure 15.12 shows an Example of DTC
Operation Timings in Chain Transfers.
Table 15.8 shows the Specifications of Control Data Write-Back Operation.
CPU clock
Address
Used by CPU
Operation Timings
Operating
Specifications of Control Data Write-Back Operation
Normal
Repeat
Example of DTC Operation Timings
Example of DTC Operation Timings in Chain Transfers
Read vector
Mode
mode
mode
Used by CPU
Incremented
Incremented Incremented Written back Written back Written back Written back
Incremented
Repeat area
Read control data
Source
Fixed
Fixed
Fixed
Oct 30, 2009
Address Control
Read vector
Incremented Written back Written back
Incremented Written back Written back Written back Written back
Repeat area
Destination
Read
Transfer data Write back control data
Fixed
Fixed
Fixed
Read control data
Write
Written back Written back
Written back Written back Written back
Written back Written back Written back
Written back Written back
Written back Written back Written back Written back
Register
DTCCTj
Control Data to be Written Back
Transfer data
Read
Register
Read control data
DTRLDj
Write
Write back control data
Not written
Not written
Not written
Register
DTSARj
back
back
back
Read
Transfer data Write back control data
Write
Written back
Written back
Not written
Not written
Not written
DTDARj
Register
back
back
back
Used by CPU
Number of
Cycles
Used by CPU
Clock
1
2
2
3
2
3
2
3
15. DTC
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