R5F2L387ANFP#U1 Renesas Electronics America, R5F2L387ANFP#U1 Datasheet - Page 231
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R5F2L387ANFP#U1
Manufacturer Part Number
R5F2L387ANFP#U1
Description
MCU 1KB FLASH 48K ROM 80-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/38Ar
Datasheet
1.R5F2L387ANFPU1.pdf
(864 pages)
Specifications of R5F2L387ANFP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
68
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 194 of 802
14.2.7
Note:
1. The OFS2 register is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a
Bits WDTRCS0 and WDTRCS1
(Watchdog Timer Refresh Acknowledgement Period Set Bit)
Bit
b0
b1
b2
b3
b4
b5
b6
b7
program.
Do not write additions to the OFS2 register. If the block including the OFS2 register is erased, the OFS2 register
is set to FFh.
When blank products are shipped, the OFS2 register is set to FFh. It is set to the written value after written by the
user.
When factory-programming products are shipped, the value of the OFS2 register is the value programmed by the
user.
For a setting example of the OFS2 register, refer to 13.3.1 Setting Example of Option Function Select Area.
Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh
acknowledgement period for the watchdog timer can be selected.
For details, refer to 15.3.1.1 Refresh Acknowledgment Period.
After Reset
WDTUFS0 Watchdog timer underflow period set bit
WDTUFS1
WDTRCS0 Watchdog timer refresh acknowledgement period
WDTRCS1
Address 0FFDBh
Symbol
Symbol
Option Function Select Register 2 (OFS2)
—
—
—
—
Bit
set bit
Reserved bits
b7
—
Oct 30, 2009
b6
—
Bit Name
b5
—
User Setting Value
b4
—
WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0
b3
(1)
b1 b0
b3 b2
Set to 1.
0 0: 03FFh
0 1: 0FFFh
1 0: 1FFFh
1 1: 3FFFh
0 0: 25%
0 1: 50%
1 0: 75%
1 1: 100%
b2
Function
b1
14. Watchdog Timer
b0
R/W
R/W
R/W
R/W
R/W
R/W
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