M38588GCSP#U0 Renesas Electronics America, M38588GCSP#U0 Datasheet - Page 73

• Manufacturer Part Number: M38588GCSP#U0
• Description: IC 740/3858 MCU QZ-ROM 42DIP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38588GCSP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 9x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3858 Group
2. Notes when selecting clock asynchronous
(1) Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(Serial I/O1 disabled), the internal transmission is running (in this
case, since pins TxD, RxD, S
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD pin and an operation failure occurs.
(2) Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
(3) Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(Serial I/O1 disabled), the internal transmission is running (in this
case, since pins TxD, RxD, S
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
3. Setting serial I/O1 control register again
Set the serial I/O1 control register again after the transmission and
the reception circuits are reset by clearing both the transmit en-
able bit and the receive enable bit to “0”.
Fig 68. Sequence of setting serial I/O1 control register
REJ03B0139-0111
page 71 of 73
receive enable bit (RE), or one of them to “1”
Set both the transmit enable bit (TE) and the
Set the bits 0 to 3 and bit 6 of the serial I/O1
Clear both the transmit enable bit (TE) and
serial I/O (Serial I/O1)
(Serial I/O1)
the receive enable bit (RE) to “0”
again
control register
Rev.1.11
CLK1
CLK1
Dec 18, 2008
, and S
, and S
RDY1
RDY1
Can be set with the
LDM instruction at
the same time
function as I/O
function as I/O
4. Data transmission control with referring to
The transmit shift register completion flag changes from “1” to “0”
with a delay of 0.5 to 1.5 shift clocks. When data transmission is
controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
5. Transmit interrupt request when transmit
When the transmit interrupt is used, set the transmit interrupt en-
able bit to transmit enabled as shown in the following sequence.
(1) Set the interrupt enable bit to “0” (disabled) with CLB instruc-
(2) Prepare serial I/O for transmission/reception.
(3) Set the interrupt request bit to “0” with CLB instruction after 1
(4) Set the interrupt enable bit to “1” (enabled).
<Reason>
When the transmission enable bit is set to “1”, the transmit buffer
empty flag and transmit shift register completion flag are set to “1”.
The interrupt request is generated and the transmission interrupt
request bit is set regardless of which of the two timings listed be-
low is selected as the timing for the transmission interrupt to be
generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
6. Transmission control when external clock
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the S
input level. Also, write the transmit data to the transmit buffer reg-
ister (serial I/O shift register) at “H” of the S
7. Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external
clock as synchronous clock, write the transmit data to the serial I/
O2 register (serial I/O shift register) at “H” of the transfer clock in-
put level.
Notes on PWM
The PWM starts after the PWM enable bit is set to enable and “L”
level is output from the PWM pin.
The length of this “L” level output is as follows:
transmit shift register completion flag
(Serial I/O1)
enable bit is set (SerialI/O1)
is selected (Serial I/O1 clock synchronous
mode)
tion.
or more instruction has been executed.
2
f(X
n + 1
n + 1
f(X
IN
)
IN
)
(s)
(s)
(Count source selection bit = “0”,
where n is the value set in the prescaler)
(Count source selection bit = “1”,
where n is the value set in the prescaler)
CLK1
input level.
CLK1