M38588GCSP#U0 Renesas Electronics America, M38588GCSP#U0 Datasheet - Page 39

• Manufacturer Part Number: M38588GCSP#U0
• Description: IC 740/3858 MCU QZ-ROM 42DIP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38588GCSP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 9x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3858 Group
(6) Programmable waveform generating mode
This mode can be selected by setting “100” to the timer Z2 operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z2 mode register (ad-
dress 002B
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(X
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(X
source.
The interrupt at an underflow is the same as the timer mode’s.
The operation is the same as the timer mode’s. Moreover the
timer outputs the data set in the output level latch (bit 4) of the
timer Z2 mode register (address 002B
each time the timer underflows.
Changing the value of the output level latch and the timer latch af-
ter an underflow makes it possible to output an optional waveform
from the CNTR
The double-function port of CNTR
cally set to the programmable waveform generating port in this
mode.
Figure 34 shows the timing chart of the programmable waveform
generating mode.
(7) Programmable one-shot generating mode
This mode can be selected by setting “101” to the timer Z2 operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z2 mode register (ad-
dress 002B
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(X
the count source.
The interrupt at an underflow is the same as the timer mode’s.
The trigger to generate one-shot pulse can be selected by the
INT
register (address 003A
selected; when it is “1”, the rising edge active is selected.
When the valid edge of the INT
request bit (bit 2) of the interrupt request register 1 (address
003C
•“H” one-shot pulse; Bit 5 of timer Z2 mode register = “0”
The output level of the CNTR
lection. When trigger generation (input signal to INT
detected, “H” is output from the CNTR
occurs, “L” is output. The “H” one-shot pulse width is set by the
setting value to the timer Z2 register low-order and high-order.
When trigger generating is detected during timer count stop, al-
REJ03B0139-0111
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Mode selection
Count source selection
Interrupt
Explanation of operation
Precautions
Mode selection
Count source selection
Interrupt
Explanation of operation
2
active edge selection bit (bit 2) of the interrupt edge selection
16
) is set to “1”.
16
16
).
).
3
pin.
CIN
16
Rev.1.11
); or f(X
). When it is “0”, the falling edge active is
3
2
pin is initialized to “L” at mode se-
CIN
pin is detected, the INT
IN
IN
) can be selected as the count
3
); or f(X
); or f(X
Dec 18, 2008
pin and port P2
3
16
pin. When an underflow
CIN
CIN
) from the CNTR
) can be selected as
) can be selected as
3
is automati-
2
2
interrupt
pin) is
3
pin
though “H” is output from the CNTR
ues because an underflow does not occur.
•“L” one-shot pulse; Bit 5 of timer Z2 mode register = “1”
The output level of the CNTR
lection. When trigger generation (input signal to INT
detected, “L” is output from the CNTR
occurs, “H” is output. The “L” one-shot pulse width is set by the
setting value to the timer Z2 low-order and high-order. When trig-
ger generating is detected during timer count stop, although “L” is
output from the CNTR
underflow does not occur.
Set the double-function port of INT
this mode.
Set the double function port of CNTR
cally set to the programmable one-shot generating port in this mode.
This mode cannot be used in low-speed mode.
If the value of the CNTR
one-shot generating enabled or generating one-shot pulse, then
the output level from CNTR
Figure 35 shows the timing chart of the programmable one-shot
generating mode.
Which write control can be selected by the timer Z2 write control
bit (bit 3) of the timer Z2 mode register (address 002B
data to both the latch and the timer at the same time or writing
data only to the latch.
When the operation “writing data only to the latch” is selected, the
value is set to the timer latch by writing data to the address of timer
Z2 and the timer is updated at next underflow. After reset release, the
operation “writing data to both the latch and the timer at the same
time” is selected, and the value is set to both the latch and the timer
at the same time by writing data to the address of timer Z2.
In the case of writing data only to the latch, if writing data to the
latch and an underflow are performed almost at the same time,
the timer value may become undefined.
A read-out of timer value is impossible in pulse period measure-
ment mode and pulse width measurement mode. In the other
modes, a read-out of timer value is possible regardless of count
operating or stopped.
However, a read-out of timer latch value is impossible.
Each interrupt active edge depends on setting of the CNTR
tive edge switch bit and the INT
When switching the count source by the timer Z2 count source selec-
tion bits, the value of timer count is altered in inconsiderable amount
owing to generating of thin pulses on the count input signals.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
To use the CNTR
ing mode bits (b2, b1, b0) of timer Z2 mode register (address
002B
Precautions
Timer Z2 write control
Timer Z2 read control
Switch of interrupt active edge of CNTR
Switch of count source
Usage of CNTR
Notes regarding all modes
16
) to “000”.
3
3
pin as normal I/O port P2
pin as normal I/O port P2
3
pin, “L” output state continues because an
3
active edge switch bit is changed during
3
pin changes.
3
pin is initialized to “H” at mode se-
2
active edge selection bit.
2
3
3
pin and port P4
pin and port P2
pin, “H” output state contin-
3
pin. When an underflow
3
3
, set timer Z2 operat-
and INT
3
3
3
2
is automati-
16
to input in
2
), writing
pin) is
3
ac-