M38588GCSP#U0 Renesas Electronics America, M38588GCSP#U0 Datasheet - Page 57

• Manufacturer Part Number: M38588GCSP#U0
• Description: IC 740/3858 MCU QZ-ROM 42DIP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38588GCSP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 9x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3858 Group
Fig. 55 Internal status at reset
REJ03B0139-0111
page 55 of 73
Note : X : Not fixed
( 1 )
( 2 )
( 3 )
( 4 )
( 5 )
( 6 )
( 7 )
( 8 )
( 9 )
( 1 0 )
( 1 1 )
( 1 2 )
( 1 3 )
( 1 4 )
( 1 5 )
( 1 6 )
( 1 7 )
( 1 8 )
( 1 9 )
( 2 0 )
( 2 1 )
( 2 2 )
( 2 3 )
( 2 4 )
( 2 5 )
( 2 6 )
( 2 7 )
( 2 8 )
( 2 9 )
( 3 0 )
( 3 1 )
( 3 2 )
( 3 3 )
( 3 4 )
P o r t P 0 ( P 0 )
P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D )
P o r t P 1 ( P 1 )
P o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D )
P o r t P 2 ( P 2 )
P o r t P 2 d i r e c t i o n r e g i s t e r ( P 2 D )
P o r t P 3 ( P 3 )
P o r t P 3 d i r e c t i o n r e g i s t e r ( P 3 D )
P o r t P 4 ( P 4 )
P o r t P 4 d i r e c t i o n r e g i s t e r ( P 4 D )
P o r t P 0 p u l l - u p c o n t r o l r e g i s t e r ( P U L L 0 )
P o r t P 1 p u l l - u p c o n t r o l r e g i s t e r ( P U L L 1 )
P o r t P 2 p u l l - u p c o n t r o l r e g i s t e r ( P U L L 2 )
P o r t P 3 p u l l - u p c o n t r o l r e g i s t e r ( P U L L 3 )
P o r t P 4 p u l l - u p c o n t r o l r e g i s t e r ( P U L L 4 )
S e r i a l I / O 2 c o n t r o l r e g i s t e r 1 ( S I O 2 C O N 1 )
S e r i a l I / O 2 c o n t r o l r e g i s t e r 2 ( S I O 2 C O N 2 )
S e r i a l I / O 2 r e g i s t e r ( S I O 2 )
T r a n s m i t / R e c e i v e b u f f e r r e g i s t e r ( T B / R B )
S e r i a l I / O 1 s t a t u s r e g i s t e r ( S I O S T S )
S e r i a l I / O 1 c o n t r o l r e g i s t e r ( S I O C O N )
U A R T c o n t r o l r e g i s t e r ( U A R T C O N )
B a u d r a t e g e n e r a t o r ( B R G )
P W M c o n t r o l r e g i s t e r ( P W M C O N )
P W M p r e s c a l e r ( P R E P W M )
P W M r e g i s t e r ( P W M )
P r e s c a l e r 1 2 ( P R E 1 2 )
T i m e r 1 ( T 1 )
T i m e r 2 ( T 2 )
T i m e r X Y m o d e r e g i s t e r ( T M )
P r e s c a l e r X ( P R E X )
T i m e r X ( T X )
P r e s c a l e r Y ( P R E Y )
T i m e r Y ( T Y )
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
Rev.1.11
Dec 18, 2008
A d d r e s s Register contents
0 0 1 C
0 0 1 D
0 0 1 A
0 0 1 B
0 0 1 E
0 0 1 F
0 0 0 0
0 0 0 1
0 0 0 2
0 0 0 3
0 0 0 4
0 0 0 5
0 0 0 6
0 0 0 7
0 0 0 8
0 0 0 9
0 0 1 0
0 0 1 1
0 0 1 2
0 0 1 3
0 0 1 4
0 0 1 5
0 0 1 6
0 0 1 7
0 0 1 8
0 0 1 9
0 0 2 0
0 0 2 1
0 0 2 2
0 0 2 3
0 0 2 4
0 0 2 5
0 0 2 6
0 0 2 7
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
0 0 0 0 0 1 1 1
X X X X X X X X
X X X X X X X X
1 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0
X X X X X X X X
X X X X X X X X
X X X X X X X X
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
F F
0 1
F F
0 0
F F
F F
F F
F F
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
Timer Z1 mode register (TZ1M)
Timer Z1 low-order (TZ1L)
Timer Z1 high-order (TZ1H)
Timer Z2 mode register (TZ2M)
Timer Z2 low-order (TZ2L)
Timer Z2 high-order (TZ2H)
T i m e r 1 2 , X c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( T 1 2 X C S S )
T i m e r Y , Z 1 c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( T Y Z 1 C S S )
T i m e r Z 2 c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( T Z 2 C S S )
AD control register (ADCON)
AD conversion register (AD)
Interrupt source selection register (INTSEL)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Processor status register
Program counter
A d d r e s s
0 0 2 8
0 0 2 9
0 0 2 A
0 0 2 B
0 0 2 C
0 0 2 D
0 0 2 E
0 0 2 F
0 0 3 0
0 0 3 4
0 0 3 5
0 0 3 6
0 0 3 8
0 0 3 9
0 0 3 A
0 0 3 B
0 0 3 C
0 0 3 D
0 0 3 E
0 0 3 F
( P S )
( P C
( P C
H
L
)
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
)
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
0 0 1 1 0 0 1 1
0 0 1 1 0 0 1 1
0 0 0 0 0 0 1 1
0 0 0 1 0 0 0 0
X X X X X X X X
0 0 1 1 1 1 1 1
0 1 0 0 1 0 0 0
X X X X X 1 X X
R e g i s t e r c o n t e n t s
F F F D
F F F C
1 6
1 6
0 0
F F
F F
0 0
F F
F F
0 0
0 0
0 0
0 0
0 0
0 0
0 0
c o n t e n t s
c o n t e n t s
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6