MC9S12XET256MAL Freescale Semiconductor, MC9S12XET256MAL Datasheet - Page 1238
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MC9S12XET256MAL
Manufacturer Part Number
MC9S12XET256MAL
Description
MCU 16BIT 256K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XET256MAL
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 12x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
112-LQFP
Cpu Family
HCS12X
Device Core Size
16b
Frequency (max)
50MHz
Interface Type
CAN/SCI/SPI
Total Internal Ram Size
16KB
# I/os (max)
91
Number Of Timers - General Purpose
25
Operating Supply Voltage (typ)
1.8/2.8/5V
Operating Supply Voltage (max)
1.98/2.9/5.5V
Operating Supply Voltage (min)
1.72/2.7/3.13V
On-chip Adc
16-chx12-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
112
Package Type
LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XET256MAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XET256MAL
Manufacturer:
FREESCALE
Quantity:
20 000
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Appendix A Electrical Characteristics
A.6.1.2
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V
the PORF bit in the CRG flags register has not been set.
A.6.1.3
When external reset is asserted for a time greater than PW
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.6.1.4
Out of stop the controller can be woken up by an external interrupt. A clock quality check as after POR is
performed before releasing the clocks to the system.
If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and
SCME = 1), the system will resume operation in self-clock mode after t
A.6.1.5
The recovery from pseudo stop and wait is essentially the same since the oscillator is not stopped in both
modes. The controller can be woken up by internal or external interrupts. After t
the interrupt vector.
1238
DD35
SRAM Data Retention
External Reset
Stop Recovery
Pseudo Stop and Wait Recovery
is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
MC9S12XE-Family Reference Manual , Rev. 1.23
RSTL
the CRG module generates an internal
fws
.
wrs
the CPU starts fetching
Freescale Semiconductor
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