R5F21266SDFP#U0 Renesas Electronics America, R5F21266SDFP#U0 Datasheet - Page 452
R5F21266SDFP#U0
Manufacturer Part Number
R5F21266SDFP#U0
Description
IC R8C/26 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/26r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21266SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21266SDFP#U0R5F21266SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 21.2
21.3.2.2
The following three workarounds should be performed in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
(2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize
• Workaround example (a):
Sep 26, 2008
write interval.
for each write interval.
As shown in Figure 21.2, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These
write operations must be completed by the beginning of period A.
following points:
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 21.2 and 21.3.
The following shows the detailed workaround examples.
Programmable waveform generation mode
Workaround Example (a) When Timer RB interrupt is Used
TRBO pin output
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
underflow signal
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
TRBIC register
Count source/
Interrupt request
is generated
prescaler
IR bit in
Page 433 of 453
(a)
sequence
Interrupt
(b)
Primary period
Interrupt request is
acknowledged
interrupt routine
Instruction in
Set the secondary and then
the primary register immediately
Ensure sufficient time
Secondary period
Period A
21. Usage Notes
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