R5F21266SDFP#U0 Renesas Electronics America, R5F21266SDFP#U0 Datasheet - Page 155
R5F21266SDFP#U0
Manufacturer Part Number
R5F21266SDFP#U0
Description
IC R8C/26 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/26r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21266SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21266SDFP#U0R5F21266SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
13. Watchdog Timer
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows
selection of count source protection mode enable or disable.
Table 13.1 lists information on the Count Source Protection Mode.
Refer to 5.7 Watchdog Timer Reset for details on the watchdog timer.
Figure 13.1 shows the Block Diagram of Watchdog Timer. Figure 13.2 shows Registers OFS and WDC. Figure 13.3
shows Registers WDTR, WDTS, and CSPR.
Figure 13.1
Table 13.1
Count source
Count operation
Count start condition
Count stop condition
Reset condition of watchdog
timer
Operation at the time of underflow Watchdog timer interrupt or
CPU clock
Internal reset signal
NOTE:
Sep 26, 2008
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
Write to WDTR register
Count Source Protection Mode
Block Diagram of Watchdog Timer
Item
Page 136 of 453
Prescaler
1/128
1/16
CPU clock
Decrement
Either of the following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Stop mode, wait mode
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
watchdog timer reset
WDC7 = 0
Count Source Protection
WDC7 = 1
fOCO-S
Mode Disabled
CSPRO = 0
CSPRO = 1
Watchdog timer
Low-speed on-chip oscillator
clock
None
Watchdog timer reset
Count Source Protection
Set to
7FFFh
Mode Enabled
(1)
CSPRO: Bit in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
13. Watchdog Timer
PM12 = 0
Watchdog timer
interrupt request
PM12 = 1
Watchdog
timer reset
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