R5F21266SDFP#U0 Renesas Electronics America, R5F21266SDFP#U0 Datasheet - Page 264
R5F21266SDFP#U0
Manufacturer Part Number
R5F21266SDFP#U0
Description
IC R8C/26 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/26r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21266SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21266SDFP#U0R5F21266SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 15.5
UARTi Transmit/Receive Control Register 0 (i = 0 or 1)
b7 b6 b5 b4
NOTE:
1.
If the BRG count source is sw itched, set the UiBRG register again.
Sep 26, 2008
b3 b2
0
Registers U0C0 to U1C0
b1 b0
Bit Symbol
UFORM
Symbol
CKPOL
TXEPT
U0C0
U1C0
CLK0
CLK1
NCH
(b2)
(b4)
Page 245 of 453
—
—
BRG count source select
bits
Reserved bit
Transmit register empty
flag
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Data output select bit
CLK polarity select bit
Transfer format select bit 0 : LSB first
(1)
Address
Bit Name
00A4h
00ACh
b1 b0
0 0 : Selects f1
0 1 : Selects f8
1 0 : Selects f32
1 1 : Do not set.
Set to 0.
0 : Data in transmit register (during transmit)
1 : No data in transmit register (transmit completed)
0 : TXDi pin is for CMOS output
1 : TXDi pin is for N-channel open drain output
0 : Transmit data is output at falling edge of transfer
1 : Transmit data is output at rising edge of transfer
1 : MSB first
clock and receive data is input at rising edge
clock and receive data is input at falling edge
After Reset
00001000b
00001000b
Function
15. Serial Interface
RW
RW
RW
RW
RW
RW
RW
RO
—
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