MC908GR4CDWE Freescale Semiconductor, MC908GR4CDWE Datasheet - Page 93

• Manufacturer Part Number: MC908GR4CDWE
• Description: IC MCU 4K FLASH 8MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR4CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.4.1 Flag Protection During Break Interrupts
6.4.2 CPU During Break Interrupts
MC68HC908GR8 — Rev 4.0
MOTOROLA
Addr.
$FE0A
$FE0B
$FE00
$FE03
$FE09
Note: Writing a logic 0 clears BW.
SIM Break Status Register
Break Status and Control
Break Address Register
Break Address Register
SIM Break Flag Control
Register Name
Register (BRKSCR)
Register (SBFCR)
High (BRKH)
Low (BRKL)
(SBSR)
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear status bits during the break state.
The CPU starts a break interrupt by:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Freescale Semiconductor, Inc.
•
•
For More Information On This Product,
Figure 6-2. I/O Register Summary
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
BCFE
BRKE
Bit 7
Bit 15
Bit 7
R
0
0
0
0
0
0
Go to: www.freescale.com
Break Module (BRK)
BRKA
= Unimplemented
14
6
R
R
0
0
0
6
0
0
13
5
R
R
0
0
0
5
0
0
0
12
4
R
R
R
1
1
0
4
0
0
0
11
3
R
R
0
0
0
3
0
0
0
= Reserved
10
2
R
R
0
0
0
2
0
0
0
Functional Description
Break Module (BRK)
NOTE
BW
1
R
0
9
0
1
0
0
0
Technical Data
Bit 0
Bit 8
Bit 0
R
R
0
0
0
0
0
0
93