MC9S08RD32PE Freescale Semiconductor, MC9S08RD32PE Datasheet - Page 67

IC MCU 32K FLASH 2K RAM 28-DIP

MC9S08RD32PE

Manufacturer Part Number
MC9S08RD32PE
Description
IC MCU 32K FLASH 2K RAM 28-DIP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08RD32PE

Core Processor
HCS08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
S08RD
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
39
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08RG60E
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S08RD32PE
Manufacturer:
Freescale Semiconductor
Quantity:
135
5.8.3
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return $00.
1. BDFR is writable only through serial background debug commands, not from user programs.
Freescale Semiconductor
BDFR
Field
0
Reset
W
R
System Background Debug Force Reset Register (SBDFR)
Background Debug Force Reset — A serial background command such as WRITE_BYTE may be used to
allow an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit
cannot be written from a user program.
0
0
7
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
= Unimplemented or Reserved
6
0
0
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Table 5-4. SBDFR Field Descriptions
0
0
5
4
0
0
Description
0
0
3
Resets, Interrupts, and System Configuration
2
0
0
0
0
1
BDFR
0
0
0
(1)
67

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