MC9S08RD32PE Freescale Semiconductor, MC9S08RD32PE Datasheet - Page 121

• Manufacturer Part Number: MC9S08RD32PE
• Description: IC MCU 32K FLASH 2K RAM 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32PE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: S08RD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08RG60E
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.6.3
The CMT modulator status and control register (CMTMSC) contains the modulator and carrier generator
enable (MCGEN), end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
(BASE), extended space (EXSPC), prescaler (CMTDIV1:CMTDIV0) bits, and the end of cycle (EOCF)
status bit.
Freescale Semiconductor
CMTDIV[1:0]
EXSPC
EOCF
BASE
Field
FSK
6:5
7
4
3
2
Reset
W
R
CMT Modulator Status and Control Register (CMTMSC)
End of Cycle Status Flag — The EOCF bit is set when:
This flag is cleared by a read of the CMTMSC register followed by an access of CMTCMD2 or CMTCMD4.
In the case where the MCGEN bit is cleared and then set before the end of the modulation cycle, EOCF will not
be set when MCGEN is set, but will be set at the end of the current modulation cycle.
0 No end of modulation cycle occurrence since flag last cleared
1 End of modulator cycle has occurred
CMT Clock Divide Prescaler — The CMT clock divide prescaler causes the CMT to be clocked at the BUS
CLOCK frequency, or the BUS CLOCK frequency divided by 1, 2, 4, or 8. Because these bits are not double
buffered, they should not be changed during a transmission.
00 Bus clock ÷ 1
01 Bus clock ÷ 2
10 Bus clock ÷ 4
11 Bus clock ÷ 8
Extended Space Enable — The EXSPC bit enables extended space operation.
0 Extended space disabled
1 Extended space enabled
Baseband Enable — When set, the BASE bit disables the carrier generator and forces the carrier output high
for generation of baseband protocols. When BASE is clear, the carrier generator is enabled and the carrier output
toggles at the frequency determined by values stored in the carrier data registers. See
“Baseband
a transmission.
0 Baseband mode disabled
1 Baseband mode enabled
FSK Mode Select — The FSK bit enables FSK operation.
0 CMT operates in time or baseband mode
1 CMT operates in FSK mode
EOCF
• The modulator is not currently active and the MCGEN bit is set to begin the initial CMT transmission.
• At the end of each modulation cycle while the MCGEN bit is set. This is recognized when a match occurs
0
7
between the contents of the space period register and the down-counter. At this time, the counter is
initialized with the (possibly new) contents of the mark period buffer, CMTCMD1 and CMTCMD2. The
space period register is loaded with the (possibly new) contents of the space period buffer, CMTCMD3 and
CMTCMD4.
Figure 8-13. CMT Modulator Status and Control Register (CMTMSC)
Mode." This bit is cleared by reset. This bit is not double buffered and should not be written to during
= Unimplemented or Reserved
CMTDIV1
6
0
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Table 8-8. CMTMSC Field Descriptions
CMTDIV0
0
5
EXSPC
4
0
Description
BASE
Carrier Modulator Transmitter (CMT) Block Description
0
3
FSK
2
0
Section 8.5.2.2,
EOCIE
0
1
MCGEN
0
0
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