S9S08SG16E1VTJ Freescale Semiconductor, S9S08SG16E1VTJ Datasheet - Page 141
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S9S08SG16E1VTJ
Manufacturer Part Number
S9S08SG16E1VTJ
Description
MCU 16K FLASH 20-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG16E1CTG.pdf
(330 pages)
Specifications of S9S08SG16E1VTJ
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-TSSOP
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Operating Supply Voltage
- 0.3 V to + 5.8 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
On-chip Dac
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
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Manufacturer
Quantity
Price
Part Number:
S9S08SG16E1VTJ SG16SVTJ
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
S9S08SG16E1VTJR
Manufacturer:
FREESCALE
Quantity:
20 000
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approximation algorithm is performed to determine the digital value of the analog signal. The result of the
conversion is transferred to ADCRH and ADCRL upon completion of the conversion algorithm.
If the bus frequency is less than the f
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the f
sample is enabled (ADLSMP=1).
The maximum total conversion time for different conditions is summarized in
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
Freescale Semiconductor
ADCK
Single or first continuous 10-bit
Single or first continuous 10-bit
Single or first continuous 10-bit
Single or first continuous 10-bit
Subsequent continuous 10-bit;
Subsequent continuous 10-bit;
Single or first continuous 8-bit
Single or first continuous 8-bit
Single or first continuous 8-bit
Single or first continuous 8-bit
Subsequent continuous 8-bit;
Subsequent continuous 8-bit;
frequency, precise sample time for continuous conversions cannot be guaranteed when long
Conversion Type
Conversion time =
f
f
BUS
BUS
The ADCK frequency must be between f
maximum to meet ADC specifications.
f
f
BUS
BUS
> f
> f
> f
> f
ADCK
ADCK
ADCK
ADCK
Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles
Table 9-13. Total Conversion Time vs. Control Conditions
/11
/11
ADCK
23 ADCK cyc
MC9S08SG32 Data Sheet, Rev. 8
8 MHz/1
frequency, precise sample time for continuous conversions
ADICLK
0x, 10
0x, 10
0x, 10
0x, 10
11
11
11
11
xx
xx
xx
xx
NOTE
ADLSMP
+
ADCK
0
0
1
1
0
0
1
1
0
0
1
1
5 bus cyc
minimum and f
8 MHz
Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
20 ADCK cycles + 5 bus clock cycles
23 ADCK cycles + 5 bus clock cycles
40 ADCK cycles + 5 bus clock cycles
43 ADCK cycles + 5 bus clock cycles
5 μs + 20 ADCK + 5 bus clock cycles
5 μs + 23 ADCK + 5 bus clock cycles
5 μs + 40 ADCK + 5 bus clock cycles
5 μs + 43 ADCK + 5 bus clock cycles
Max Total Conversion Time
= 3.5 μs
ADCK
17 ADCK cycles
20 ADCK cycles
37 ADCK cycles
40 ADCK cycles
Table
9-13.
141
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