MC9S08QG84CFFER Freescale Semiconductor, MC9S08QG84CFFER Datasheet - Page 71

• Manufacturer Part Number: MC9S08QG84CFFER
• Description: IC MCU 8BIT 8K FLASH 16-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG84CFFER

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-QFN
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 512 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Mounting Style: SMD/SMT
• Height: 1 mm
• Interface Type: I2C, SCI, SPI
• Length: 5 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Width: 5 mm
• For Use With: DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1
5.8.3
This high page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
Freescale Semiconductor
BDFR is writable only through serial background debug commands, not from user programs.
Reset:
BDFR
Field
0
W
R
System Background Debug Force Reset Register (SBDFR)
Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program. To enter user mode, PTA4/ACMPO/BKGD/MS must be high immediately after
issuing WRITE_BYTE command. To enter BDM, PTA4/ACMPO/BKGD/MS must be low immediately after issuing
WRITE_BYTE command. See
0
0
7
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
= Unimplemented or Reserved
0
0
6
Table 5-5. SBDFR Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
0
0
5
Table A-9., “Control
0
0
4
Description
Timing,” for more information.
Chapter 5 Resets, Interrupts, and General System Control
3
0
0
0
0
2
0
0
1
BDFR
0
0
0
1
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