ST72F561R9TA STMicroelectronics, ST72F561R9TA Datasheet - Page 135

• Manufacturer Part Number: ST72F561R9TA
• Description: IC MCU 8BIT 60K FLASH 64-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561R9TA

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
BAUD RATE REGISTER (SCIBRR)
Read/Write
Reset Value: 0000 0000 (00h)
Note: When LIN slave mode is disabled, the SCI-
BRR register controls the conventional baud rate
generator.
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and
SCP0 bits define the total division applied to the
bus clock to yield the transmit rate clock in conven-
tional Baud Rate Generator mode.
SCP1
7
PR Prescaling factor
SCP0
13
SCT2
1
3
4
SCT1
SCT0
SCP1
SCR2 SCR1 SCR0
0
1
SCP0
0
1
0
1
0
Bits 2:0 = SCR[2:0] SCI Receiver rate divider
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
RR dividing factor
TR dividing factor
128
128
16
32
64
16
32
64
1
2
4
8
1
2
4
8
SCR2
SCT2
0
1
0
1
SCR1
SCT1
0
1
0
1
0
1
0
1
ST72561
SCR0
SCT0
135/265
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1