ST72F321AR9TA STMicroelectronics, ST72F321AR9TA Datasheet - Page 88

• Manufacturer Part Number: ST72F321AR9TA
• Description: IC MCU 8BIT 60KB FLASH 64-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F321AR9TA

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST72321Rx ST72321ARx ST72321Jx
10.5 SERIAL PERIPHERAL INTERFACE (SPI)
10.5.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
10.5.2 Main Features
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Figure 53. Serial Peripheral Interface Block Diagram
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Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
Six master mode frequencies (f
f
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun
flags
MOSI
MISO
CPU
SCK
SS
/2 max. slave mode frequency (see note)
SOD
bit
SPIDR
8-Bit Shift Register
Read Buffer
SERIAL CLOCK
CPU
GENERATOR
CONTROL
MASTER
/4 max.)
Data/Address Bus
Read
Write
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
10.5.3 General Description
Figure 53
(SPI) block diagram. There are 3 registers:
The SPI is connected to external devices through
4 pins:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
7
SPIE
SPIF WCOL
7
SPE
shows the serial peripheral interface
CONTROL
SPR2
OVR
STATE
SPI
Interrupt
request
MODF
MSTR
CPOL
0
CPHA
SOD
SS
SPICR
SPICSR
SSM
SPR1
0
1
SPR0
SSI
0
0