Z8F4822AR020EC Zilog, Z8F4822AR020EC Datasheet - Page 161

• Manufacturer Part Number: Z8F4822AR020EC
• Description: IC ENCORE MCU FLASH 48K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F4822AR020EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 269-3289

PS019921-0308
Write Transaction with a 10-Bit Address
7. The I
8. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is
9. Software responds by writing the second byte of address into the contents of the I
10. The I
11. If the I
12. The I
13. The I
14. Software responds by setting the STOP bit in the I
15. Software polls the STOP bit of the I
16. Software checks the ACK bit of the I
Figure 30
indicate data transferred from the I
data transferred from the slaves to the I
S
Slave Address
Figure 30. 10-Bit Addressed Slave Data Transfer Format
register.
asserted.
Data register.
signal.
high period of SCL the I
Continue with
If the slave does not acknowledge the first address byte, the I
NCKI bit and clears the ACK bit in the I
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I
NCKI bits. The transaction is complete (ignore following steps).
register (2nd byte of address).
bit has been sent, the Transmit interrupt is asserted.
be cleared at the same time.
bit when the transaction is completed (STOP condition has been sent).
ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI
interrupt do not occur because the STOP bit was set.
1st 7 bits
2
2
2
2
displays the data transfer format for a 10-bit addressed slave. Shaded regions
C Controller loads the I
C Controller shifts the rest of the first byte of address and write bit out the SDA
C Controller loads the I
C Controller shifts the second address byte out the SDA signal. After the first
2
C slave sends an acknowledge by pulling the SDA signal low during the next
2
C Controller sends the STOP condition on the bus and clears the STOP and
step
W = 0 A
12.
2
C Controller sets the ACK bit in the I
2
2
2
C Shift register with the contents of the I
C Shift register with the contents of the I
C Controller to slaves and unshaded regions indicate
Slave Address
2
2
C Controller.
C Control register. Hardware deasserts the STOP
2
2nd Byte
C Status register. If the slave acknowledged, the
2
C Status register. Software responds to the
2
C Control register. The TXI bit can
Z8 Encore! XP
A Data A Data A/A P/S
Product Specification
2
C Controller sets the
2
C Status register.
®
F64XX Series
2
2
C Data
C Data
I2C Controller
2
C
147