Z8F4822AR020EC Zilog, Z8F4822AR020EC Datasheet - Page 127

• Manufacturer Part Number: Z8F4822AR020EC
• Description: IC ENCORE MCU FLASH 48K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F4822AR020EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 269-3289

Table 55. UART Status 1 Register (UxSTAT1)
Table 56. UART Control 0 Register (UxCTL0)
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
UART Control 0 and Control 1 Registers
TEN
7
7
Reserved—Must be 0.
NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive
Data register resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
MPRX—Multiprocessor Receive
Returns the value of the last multiprocessor bit received. Reading from the UART Receive
Data register resets this bit to 0.
The UART Control 0 and Control 1 registers (see
figure the properties of the UART’s transmit and receive operations. The UART Control
registers must not been written while the UART is enabled.
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is
enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
REN
6
6
R
CTSE
5
5
Reserved
PEN
F44H and F4CH
F42H and F4AH
4
4
R/W
0
0
PSEL
3
3
Table 56
R/W
Z8 Encore! XP
SBRK
2
and
2
Table 57
Product Specification
NEWFRM
STOP
1
1
®
on page 114) con-
F64XX Series
R
MPRX
LBEN
0
0
UART
113