Z8F0822PJ020SG Zilog, Z8F0822PJ020SG Datasheet - Page 77

• Manufacturer Part Number: Z8F0822PJ020SG
• Description: IC ENCORE MCU FLASH 8K 28DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0822PJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Controller Family/series: Z8
• No. Of I/o's: 19
• Ram Memory Size: 1KB
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: Z8F082xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4208; Z8F0822PJ020SG

Table 29. IRQ0 Enable High Bit Register (IRQ0ENH)
Table 30. IRQ0 Enable Low Bit Register (IRQ0ENL)
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
IRQ1 Enable High and Low Bit Registers
7
Reserved
Reserved
7
Reserved—Must be 0
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
I2CENH—I
SPIENH—SPI Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
Reserved—Must be 0
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
I2CENL—I
SPIENL—SPI Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
Table 31
Registers
Interrupt Request 1 Register. Priority is generated by setting bits in each register.
6
T1ENH
T1ENL
describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit
(Table 32
6
2
2
C Interrupt Request Enable Low Bit
C Interrupt Request Enable High Bit
5
and
T0ENH
T0ENL
5
Table
33) form a priority encoded enabling for interrupts in the
4
U0RENH
U0RENL
4
FC1H
FC2H
R/W
R/W
0
0
3
U0TENH
U0TENL
3
2
Z8 Encore! XP
I2CENH
I2CENL
2
Product Specification
1
SPIENH
SPIENL
1
®
Interrupt Controller
F0822 Series
0
ADCENH
ADCENL
0
64