Z8F0822PJ020SG Zilog, Z8F0822PJ020SG Datasheet - Page 196

• Manufacturer Part Number: Z8F0822PJ020SG
• Description: IC ENCORE MCU FLASH 8K 28DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0822PJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Controller Family/series: Z8
• No. Of I/o's: 19
• Ram Memory Size: 1KB
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: Z8F082xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4208; Z8F0822PJ020SG

Table 95. OCD Status Register (OCDSTAT)
PS022517-0508
BITS
FIELD
RESET
R/W
OCD Status Register
IDLE
automatically set to 1. If this bit is set, the OCDCNTR register does not count when the
CPU is running.
0 = OCDCNTR is setup as counter
1 = OCDCNTR generates hardware break when PC == OCDCNTR
BRKZRO—Break when OCDCNTR ==
If this bit is set, then the OCD automatically sets the DBGMODE bit when the OCD-
CNTR register counts down to
when the part leaves DEBUG Mode.
0 = OCD does not generate BRK when OCDCNTR decrements to 0000H
1 = OCD sets DBGMODE to 1 when OCDCNTR decrements to 0000H
Reserved
These bits are reserved and must be 0.
RST—Reset
Setting this bit to 1 resets the Z8 Encore! XP
through a normal POR sequence with the exception that the OCD is not reset. This bit is
automatically cleared to 0 when the reset finishes.
0 = No effect.
1 = Reset the Z8 Encore! XP F0822 Series device.
The OCD Status register reports status information about the current state of the debugger
and the system.
IDLE—CPU Idling
This bit is set if the part is in DEBUG mode (DBGMODE is 1), or if a BRK instruction
occurred since the last time OCDCTL was written. This can be used to determine if the
CPU is running or if it is idling.
0 = The eZ8 CPU is running.
1 = The eZ8 CPU is either stopped or looping on a BRK instruction.
HALT—HALT Mode
0 = The device is not in HALT mode.
1 = The device is in HALT mode.
7
HALT
6
RPEN
5
0000H
4
. If this bit is set, the OCDCNTR register is not reset
R
0
0000H
®
F0822 Series device. The device goes
3
Reserved
Z8 Encore! XP
2
Product Specification
1
®
On-Chip Debugger
F0822 Series
0
183