ST7FLITE39F2B6 STMicroelectronics, ST7FLITE39F2B6 Datasheet - Page 70

• Manufacturer Part Number: ST7FLITE39F2B6
• Description: IC MCU 8BIT 8K FLASH 20DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE39F2B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ST7FLITE3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• For Use With: 497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-6398 - BOARD EVAL ST7FLITE39/STM1403497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5514 - EVAL BOARD THERMO CONTROL REFRIG497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5634-5

ST7LITE3xF2
DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
Bit 4 = OVFIE2 Overflow interrupt 2 enable
This bit is read/write by software and controls the
overflow interrupt of counter2.
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
Bit 3 = OVF2 Overflow Flag.
This bit is set by hardware and cleared by software
by reading the ATCSR2 register. It indicates the
transition of the counter2 from FFFh to ATR2 val-
ue.
0: No counter overflow occurred
1: Counter overflow occurred
Bit 2 = ENCNTR2 Enable counter2
This bit is read/write be software and switches the
second counter CNTR2. If this bit is set, PWM2
and PWM3 will be generated using CNTR2.
0: CNTR2 stopped.
1: CNTR2 starts running.
Bit 1= TRAN2 Transfer enable2
This bit is read/write by software, cleared by hard-
ware after each completed transfer and set by
hardware after reset. It controls the transfers on
CNTR2.
It allows the value of the Preload DCRx registers
to be transferred to the Active DCRx registers after
the next overflow event.
The OPx bits are transferred to the shadow OPx
bits in the same way.
(Only DCR2/DCR3 can be controlled with this bit)
Bit 0 = TRAN1 Transfer enable 1
This bit is read/write by software, cleared by hard-
ware after each completed transfer and set by
hardware after reset. It controls the transfers on
CNTR1. It allows the value of the Preload DCRx
registers to be transferred to the Active DCRx reg-
isters after the next overflow event.
The OPx bits are transferred to the shadow OPx
bits in the same way.
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1
AUTORELOAD REGISTER2 (ATR2H)
Read / Write
Reset Value: 0000 0000 (00h)
AUTORELOAD REGISTER (ATR2L)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 11:0 = ATR2[11:0] Autoreload Register 2.
This is a 12-bit register which is written by soft-
ware. The ATR2 register value is automatically
loaded into the upcounter CNTR2 when an over-
flow of CNTR2 occurs. The register value is used
to
ENCNTR2 is set.
DEAD TIME GENERATOR REGISTER (DTGR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7 = DTE Dead Time Enable
This bit is read/write by software. It enables a dead
time generation on PWM0/PWM1.
0: No Dead time insertion.
1: Dead time insertion enabled.
Bit 6:0 = DT[6:0] Dead Time Value
These bits are read/write by software. They define
the dead time inserted between PWM0/PWM1.
Dead time is calculated as follows:
Dead Time = DT[6:0] x Tcounter1
ATR7
DTE
15
0
7
7
set
ATR6
DT6
0
the
ATR5
DT5
0
PWM2/PWM3
ATR4
DT4
0
ATR11 ATR10 ATR9
ATR3
DT3
frequency
ATR2
DT2
ATR1
DT1
when
ATR0
ATR8
DT0
0
0
8