ST7FLITE39F2B6 STMicroelectronics, ST7FLITE39F2B6 Datasheet - Page 48

• Manufacturer Part Number: ST7FLITE39F2B6
• Description: IC MCU 8BIT 8K FLASH 20DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE39F2B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ST7FLITE3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• For Use With: 497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-6398 - BOARD EVAL ST7FLITE39/STM1403497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5514 - EVAL BOARD THERMO CONTROL REFRIG497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5634-5

ST7LITE3xF2
I/O PORTS (Cont’d)
Figure 31. I/O Port General Block Diagram
Table 9. I/O Port Mode Options
Legend: NI - not implemented
Note 1: The diode to V
true open drain pads. A local protection between
48/173
1
Input
Output
REGISTER
ACCESS
INTERRUPT
REQUEST (ei
EXTERNAL
Off - implemented not activated
On - implemented and activated
DDR SEL
OR SEL
DR SEL
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Open Drain (logic level)
True Open Drain
Configuration Mode
DDR
OR
DR
x
)
SENSITIVITY
SELECTION
DD
ALTERNATE
OUTPUT
From on-chip periphera
ALTERNATE
ENABLE
BIT
If implemented
is not implemented in the
1
0
Combinational
Logic
l
1
0
FROM
OTHER
BITS
Pull-Up
Note: Refer to the Port Configuration
table for device specific information.
Off
On
Off
NI
the pad and V
vice against positive stress.
Note 2: For further details on port configuration,
please refer to
N-BUFFER
PULL-UP
CONDITION
P-Buffer
Off
On
Off
NI
OL
Table 11
SCHMITT
TRIGGER
CMOS
is implemented to protect the de-
V
DD
NI (see note 1)
and
to V
On
Table 12 on page
DD
P-BUFFER
(see table below)
To on-chip peripheral
V
Diodes
DD
DIODES
(see table below)
PULL-UP
(see table below)
ALTERNATE
ANALOG
INPUT
to V
INPUT
PAD
On
SS
51.