Z8F012ASB020EG Zilog, Z8F012ASB020EG Datasheet - Page 59

• Manufacturer Part Number: Z8F012ASB020EG
• Description: IC ENCORE XP MCU FLASH 1K 8SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F012ASB020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: Z8F012Ax
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4038; Z8F012ASB020EG

Table 20. Port A–D Alternate Function Sub-Registers (PxAF)
Table 21. Port A–D Output Control Sub-Registers (PxOC)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS022825-0908
Caution:
POC7
R/W
AF7
If 02H in Port A–D Address Register, accessible through the Port A–D Control Register
If 03H in Port A–D Address Register, accessible through the Port A–D Control Register
7
7
Set 1 Sub-Registers
Alternate Function Set 2 Sub-Registers
page 38 to determine the alternate function associated with each port pin.
AF[7:0]—Port Alternate Function enabled
0 = The port pin is in normal mode and the DDx bit in the Port A–D Data Direction
sub-register determines the direction of the pin.
1 = The alternate function selected through Alternate Function Set sub-registers is
enabled. Port pin operation is controlled by the alternate function.
Port A–D Output Control Sub-Registers
The Port A–D Output Control sub-register
Control register by writing
Port A–D Output Control sub-registers to 1 configures the specified port pins for open-
drain operation. These sub-registers affect the pins directly and, as a result, alternate func-
tions are also affected.
POC[7:0]—Port Output Control
These bits function independently of the alternate function bit and always disable the
drains if set to 1.
0 = The source current is enabled for any output mode (unless overridden by the alternate
Do not enable alternate functions for GPIO port pins for which there is no
associated alternate function. Failure to follow this guideline can result in
unpredictable operation.
POC6
R/W
AF6
6
6
00H (Ports A–C); 01H (Port D); 04H (Port A of 8-pin device)
on page 50,
POC5
R/W
AF5
5
5
00H (Ports A-C); 01H (Port D)
03H
to the Port A–D Address register. Setting the bits in the
GPIO Alternate Functions
POC4
R/W
AF4
4
4
on page 51
R/W
(Table
POC3
R/W
AF3
3
3
21) is accessed through the Port A–D
.
See
Z8 Encore! XP
GPIO Alternate Functions
POC2
R/W
AF2
on page 38, and
2
2
General-Purpose Input/Output
Product Specification
POC1
R/W
AF1
1
1
®
F082A Series
Port A–D
POC0
R/W
AF0
on
0
0
48