Z8F012ASB020EG Zilog, Z8F012ASB020EG Datasheet - Page 135

• Manufacturer Part Number: Z8F012ASB020EG
• Description: IC ENCORE XP MCU FLASH 1K 8SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F012ASB020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: Z8F012Ax
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4038; Z8F012ASB020EG

PS022825-0908
Caution:
Continuous Conversion
4. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
5. When the conversion is complete, the ADC control logic performs the following
6. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
When configured for continuous conversion, the ADC continuously performs an
analog-to-digital conversion on the selected analog input. Each new data value over-writes
the previous value stored in the ADC Data registers. An interrupt is generated after each
conversion.
Follow the steps below for setting up the ADC and initiating continuous conversion:
1. Enable the desired analog input by configuring the general-purpose I/O pins for
2. Write the
In CONTINUOUS mode, ADC updates are limited by the input signal bandwidth of the
ADC and the latency of the ADC and its digital filter. Step changes at the input are not
immediately detected at the next output from the ADC. The response of the ADC (in all
modes) is limited by the input signal bandwidth and the latency.
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power up
before beginning the 5129 cycle conversion.
operations:
powered-down.
alternate function. This action disables the digital input and output driver.
–
–
–
–
–
–
–
–
If the internal voltage reference must be output to a pin, set the
1. The internal voltage reference must be enabled in this case.
Write the
voltage reference level or to disable the internal reference. The
contained in the
Set CEN to 1 to start the conversion.
13-bit two’s-complement result written to {ADCD_H[7:0], ADCD_L[7:3]}.
Sends an interrupt request to the Interrupt Controller denoting conversion
complete.
CEN resets to 0 to indicate the conversion is complete.
Write to
mode, as well as unbuffered or buffered mode.
Write the
voltage reference level or to disable the internal reference. The
contained in the
ADC Control/Status Register 1
BUFMODE
REFSELL
REFSELH
ADC Control/Status Register
ADC Control Register
[2:0] to select SINGLE-ENDED or DIFFERENTIAL
bit of the pair {
bit of the pair {
to configure the ADC.
REFSELH
REFSELH
0.
Z8 Encore! XP
,
,
REFSELL
REFSELL
1.
Product Specification
Analog-to-Digital Converter
} to select the internal
} to select the internal
®
F082A Series
REFSELH
REFSELL
REFEXT
bit to
bit is
bit is
124