Z8F012ASB020EG Zilog, Z8F012ASB020EG Datasheet - Page 196

• Manufacturer Part Number: Z8F012ASB020EG
• Description: IC ENCORE XP MCU FLASH 1K 8SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F012ASB020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: Z8F012Ax
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4038; Z8F012ASB020EG

Table 107. OCD Status Register (OCDSTAT)
PS022825-0908
BITS
FIELD
RESET
R/W
OCD Status Register
DBG
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a
Debug Acknowledge character (
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
Reserved—Must be 0.
RST—Reset
Setting this bit to 1 resets the Z8F04xA family device. The device goes through a normal
Power-On Reset sequence with the exception that the On-Chip Debugger is not reset. This
bit is automatically cleared to 0 at the end of reset.
0 = No effect.
1 = Reset the Flash Read Protect Option Bit device.
The OCD Status register reports status information about the current state of the debugger
and the system.
DBG—Debug Status
0 = NORMAL mode
1 = DEBUG mode
HALT—HALT Mode
0 = Not in HALT mode
1 = In HALT mode
FRPENB—Flash Read Protect Option Bit Enable
0 = FRP bit enabled, that allows disabling of many OCD commands
1 = FRP bit has no effect
Reserved—Must be 0
R
7
0
HALT
R
6
0
FRPENB
R
5
0
FFH
R
4
0
) to the host when a Breakpoint occurs.
R
3
0
Z8 Encore! XP
Reserved
R
2
0
Product Specification
R
1
0
®
On-Chip Debugger
F082A Series
R
0
0
185