Z8F0113PJ005SG Zilog, Z8F0113PJ005SG Datasheet - Page 92
Z8F0113PJ005SG
Manufacturer Part Number
Z8F0113PJ005SG
Description
IC ENCORE MCU FLASH 1K 28DIP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F0223SB005SG.pdf
(247 pages)
Specifications of Z8F0113PJ005SG
Core Processor
Z8
Core Size
8-Bit
Speed
5MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
269-3995
Z8F0113PJ005SG
Z8F0113PJ005SG
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Table 54. Timer 0–1 PWM Low Byte Register (TxPWML)
Table 55. Timer 0–1 Control Register 0 (TxCTL0)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS024314-0308
Timer 0–1 Control Registers
TMODEHI
R/W
R/W
7
0
7
0
PWMH and PWML—Pulse-Width Modulator High and Low Bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOL bit in the Timer Control Register (TxCTL1)
register.
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when
operating in CAPTURE or CAPTURE/COMPARE modes.
Time 0–1 Control Register 0
The Timer Control Register 0 (TxCTL0) and Timer Control Register 1 (TxCTL1)
determine the timer operating mode. It also includes a programmable PWM deadband
delay, two bits to configure timer interrupt definition, and a status bit to identify if the
most recent timer interrupt is caused by an input Capture event.
TMODEHI—Timer Mode High Bit
This bit along with the TMODE field in TxCTL1 register determines the operating mode
of the timer. This is the most-significant bit of the Timer mode selection value. See the
TxCTL1 register description for more details.
TICONFIG—Timer Interrupt Configuration
This field configures timer interrupt definition.
R/W
R/W
6
0
6
0
TICONFIG
R/W
R/W
5
0
5
0
Reserved
R/W
R/W
4
0
4
0
F05H, F0DH
F06H, F0EH
PWML
R/W
R/W
3
0
3
0
Z8 Encore! XP
PWMD
R/W
R/W
2
0
2
0
Product Specification
R/W
R/W
1
0
1
0
®
F0823 Series
INPCAP
R/W
R/W
0
0
0
0
Timers
82
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