Z8F0113PJ005SG Zilog, Z8F0113PJ005SG Datasheet - Page 70
Z8F0113PJ005SG
Manufacturer Part Number
Z8F0113PJ005SG
Description
IC ENCORE MCU FLASH 1K 28DIP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F0223SB005SG.pdf
(247 pages)
Specifications of Z8F0113PJ005SG
Core Processor
Z8
Core Size
8-Bit
Speed
5MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
269-3995
Z8F0113PJ005SG
Z8F0113PJ005SG
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Table 36. Interrupt Request 2 Register (IRQ2)
Table 38. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS024314-0308
IRQ0 Enable High and Low Bit Registers
Reserved
R/W
R/W
7
0
7
0
Reserved—Must be 0
PCxI—Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x
1 = An interrupt request from GPIO Port C pin x is awaiting service
where x indicates the specific GPIO Port C pin number (0–3)
Table 37
registers
Interrupt Request 0 register. Priority is generated by setting bits in each register.
Table 37. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority
where x indicates the register bits from 0–7.
0
0
1
1
T1ENH
(Table 38
describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit
R/W
R/W
6
0
6
0
Reserved
and
T0ENH
0
1
0
1
R/W
R/W
Table
5
0
5
0
39) form a priority encoded enabling for interrupts in the
Disabled
Level 1
Level 2
Level 3
U0RENH
R/W
R/W
4
0
4
0
FC6H
FC1H
U0TENH
PC3I
R/W
R/W
Description
Disabled
Low
Nominal
High
3
0
3
0
Reserved Reserved
Z8 Encore! XP
PC2I
R/W
R/W
2
0
2
0
Product Specification
PC1I
R/W
R/W
1
0
1
0
®
Interrupt Controller
F0823 Series
ADCENH
PC0I
R/W
R/W
0
0
0
0
60
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