LH7A400N0G000B5;55 NXP Semiconductors, LH7A400N0G000B5;55 Datasheet - Page 7

• Manufacturer Part Number: LH7A400N0G000B5;55
• Description: IC ARM9 BLUESTREAK MCU 256BGA
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7Ar

Specifications of LH7A400N0G000B5;55

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, Microwire, MMC, SmartCard, SPI, SSI, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 60
• Ram Memory Size: 80KB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Digital Ic Case Style: BGA
• Processor Series: LH7A4
• Core: ARM9TDMI
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4334; 935285038557

32-Bit System-on-Chip
Preliminary data sheet
BGA
C13
G10
D11
M16
N14
M13
H16
H14
G16
G14
G13
D15
C16
D10
C10
C14
E12
B12
B11
K16
K15
K14
F16
F14
E16
E13
F11
B16
A15
A13
B10
A10
PIN
J16
J14
G8
A8
D8
C8
G9
F8
J8
J9
LFBGA
C12
M15
M16
G15
G10
G11
B13
B14
A14
B12
A12
K12
K13
K16
H15
H10
H12
F16
E16
F13
E14
D15
C16
C15
C14
B15
E11
A10
A11
B10
C13
PIN
L15
J13
J11
J16
D8
C8
D9
B7
A7
F8
E9
D26
D27
D28
D29
D30
D31
A0/nWE1
A1/nWE2
A2/SA0
A3/SA1
A4/SA2
A5/SA3
A6/SA4
A7/SA5
A8/SA6
A9/SA7
A10/SA8
A11/SA9
A12/SA10
A13/SA11
A14/SA12
A15/SA13
A16/SB0
A17/SB1
A18
A19
A20
A21
A22
A23
A24
A25/SCIO
A26/SCCLK
A27/SCRST
nOE
nWE0
nWE3
CS6/SCKE1_2
CS7/SCKE0
SCKE3
SCLK
nSCS0
SIGNAL
Data Bus
• Asynchronous Address Bus
• Asynchronous Memory Write Byte Enable 1
• Asynchronous Address Bus
• Asynchronous Memory Write Byte Enable 2
• Asynchronous Address Bus
• Synchronous Address Bus
• Async Address Bus
• Sync Device Bank Address 0
• Async Address Bus
• Sync Device Bank Address 1
Asynchronous Address Bus
• Async Memory Address Bus
• Smart Card Interface I/O (Data)
• Async Memory Address Bus
• Smart Card Interface Clock
• Async Memory Address Bus
• Smart Card Interface Reset
Async Memory Output Enable
Async Memory Write Byte Enable 0
Async Memory Write Byte Enable 3
• Async Memory Chip Select 6
• Sync Memory Clock Enable 1 or 2
• Async Memory Chip Select 7
• Sync Memory Clock Enable 0
Sync Memory Clock Enable 3
Sync Memory Clock
Sync Memory Chip Select 0
Table 3. Functional Pin List (Cont’d)
DESCRIPTION
Rev. 01 — 16 July 2007
NXP Semiconductors
LOW: CS6
LOW: CS7
LOW: A25
LOW: A26
LOW: A27
RESET
STATE
HIGH:
nWE1
HIGH:
nWE2
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
No Change
No Change
No Change
No Change
No Change
No Change
No Change
STANDBY
STATE
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
OUTPUT
DRIVE
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
8 mA
I/O NOTES
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LH7A400
2
7