LPC2478FET208,551 NXP Semiconductors, LPC2478FET208,551 Datasheet - Page 73
![IC ARM7 MCU 512K LCD 208-TFBGA](/photos/12/32/123264/lpc2478fet208-s_sml.jpg)
LPC2478FET208,551
Manufacturer Part Number
LPC2478FET208,551
Description
IC ARM7 MCU 512K LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2478FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4364
935284072551
LPC2478FET208-S
935284072551
LPC2478FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
7. Memory bank select
UM10237_4
User manual
6.1 Low-power SDRAM Deep-sleep Mode
6.2 Low-power SDRAM partial array refresh
Self-refresh mode can be entered by software by setting the SREFREQ bit in the
EMCDynamicControl Register and polling the SREFACK bit in the EMCStatus Register.
Any transactions to memory that are generated while the memory controller is in
self-refresh mode are rejected and an error response is generated to the AHB bus.
Clearing the SREFREQ bit in the EMCDynamicControl Register returns the memory to
normal operation. See the memory data sheet for refresh requirements.
Note: The static memory can be accessed as normal when the SDRAM memory is in
self-refresh mode.
The EMC supports JEDEC low-power SDRAM deep-sleep mode. Deep-sleep mode can
be entered by setting the deep-sleep mode (DP) bit, the dynamic memory clock enable bit
(CE), and the dynamic clock control bit (CS) in the EMCDynamicControl register. The
device is then put into a low-power mode where the device is powered down and no
longer refreshed. All data in the memory is lost.
The EMC supports JEDEC low-power SDRAM partial array refresh. Partial array refresh
can be programmed by initializing the SDRAM memory device appropriately. When the
memory device is put into self-refresh mode only the memory banks specified are
refreshed. The memory banks that are not refreshed lose their data contents.
Eight independently-configurable memory chip selects are supported:
Static memory chip select ranges are each 16 megabytes in size, while dynamic memory
chip selects cover a range of 256 megabytes each.
of the chip selects.
Table 65.
[1]
Chip select pin
CS0
CS1
CS2
CS3
DYCS0
DYCS1
DYCS2
DYCS3
•
•
Pins CSn3 to CSn0 are used to select static memory devices.
Pins DYCSn3 to DYCSn0 are used to select dynamic memory devices.
For LPC2458, see
Memory bank selection
Address range
0x8000 0000 - 0x80FF FFFF
0x8100 0000 - 0x81FF FFFF
0x8200 0000 - 0x82FF FFFF
0x8300 0000 - 0x83FF FFFF
0xA000 0000 - 0xAFFF FFFF
0xB000 0000 - 0xBFFF FFFF
0xC000 0000 - 0xCFFF FFFF
0xD000 0000 - 0xDFFF FFFF
Table
Rev. 04 — 26 August 2009
2–14.
Chapter 5: LPC24XX External Memory Controller (EMC)
[1]
Table 5–65
Memory type
Static
Static
Static
Static
Dynamic
Dynamic
Dynamic
Dynamic
shows the address ranges
UM10237
© NXP B.V. 2009. All rights reserved.
Size of range
16 MB
16 MB
16 MB
16 MB
256 MB
256 MB
256 MB
256 MB
73 of 792
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