LPC2478FET208,551 NXP Semiconductors, LPC2478FET208,551 Datasheet - Page 643
![IC ARM7 MCU 512K LCD 208-TFBGA](/photos/12/32/123264/lpc2478fet208-s_sml.jpg)
LPC2478FET208,551
Manufacturer Part Number
LPC2478FET208,551
Description
IC ARM7 MCU 512K LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2478FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4364
935284072551
LPC2478FET208-S
935284072551
LPC2478FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
6.5 PWM Capture Control Register (PWM0CCR - 0xE001 4028 and
Table 561: Match Control Register (PWM0MCR - address 0xE000 4014 and PWM1MCR -
PWM1CCR 0xE001 8028)
The Capture Control register is used to control whether any of the Capture registers is
loaded with the value in the Timer Counter when a capture event occurs on PCAP0[0] or
PCAP1[1:0], and whether an interrupt is generated by the capture event. Setting both the
rising and falling bits at the same time is a valid configuration, resulting in a capture event
for both edges. In the descriptions below, “n” represents the Timer number, 0 or 1.
Note: If Counter mode is selected for a particular PCAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other two PCAP inputs.
Table 562: PWM Capture Control Register (PWM0CCR - address 0xE001 4028 and PWM1CCR
Bit
16
17
18
19
20
31:21 -
Bit
0
1
2
Symbol
Capture on
PCAPn.0
rising edge
Capture on
PCAPn.0
falling edge
Interrupt on
PCAPn.0
event
Symbol
PWMMR5R 1
PWMMR6I
PWMMR6R 1
PWMMR5S 1
PWMMR6S 1
address 0xE000 8014) bit description
address 0xE001 8028) bit description
Value Description
0
0
1
0
0
0
Value Description
0
1
0
1
0
1
Rev. 04 — 26 August 2009
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
Reset on PWMMR5: the PWMTC will be reset if PWMMR5
matches it.
This feature is disabled.
Stop on PWMMR5: the PWMTC and PWMPC will be stopped
and PWMTCR[0] will be set to 0 if PWMMR5 matches the
PWMTC.
This feature is disabled
Interrupt on PWMMR6: an interrupt is generated when
PWMMR6 matches the value in the PWMTC.
This interrupt is disabled.
Reset on PWMMR6: the PWMTC will be reset if PWMMR6
matches it.
This feature is disabled.
Stop on PWMMR6: the PWMTC and PWMPC will be stopped
and PWMTCR[0] will be set to 0 if PWMMR6 matches the
PWMTC.
This feature is disabled
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
This feature is disabled.
A synchronously sampled rising edge on the PCAPn.0 input
will cause CR0 to be loaded with the contents of the TC.
This feature is disabled.
A synchronously sampled falling edge on PCAPn.0 will cause
CR0 to be loaded with the contents of TC.
This feature is disabled.
A CR0 load due to a PCAPn.0 event will generate an
interrupt.
UM10237
© NXP B.V. 2009. All rights reserved.
643 of 792
Reset
Value
0
0
0
0
0
NA
Reset
Value
0
0
0
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