LPC2478FET208,551 NXP Semiconductors, LPC2478FET208,551 Datasheet - Page 240
![IC ARM7 MCU 512K LCD 208-TFBGA](/photos/12/32/123264/lpc2478fet208-s_sml.jpg)
LPC2478FET208,551
Manufacturer Part Number
LPC2478FET208,551
Description
IC ARM7 MCU 512K LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2478FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4364
935284072551
LPC2478FET208-S
935284072551
LPC2478FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- Current page: 240 of 792
- Download datasheet (5Mb)
NXP Semiconductors
UM10237_4
User manual
7.4.3 Interrupt Clear Register (IntClear - 0xFFE0 0FE8)
7.4.4 Interrupt Set Register (IntSet - 0xFFE0 0FEC)
Table 229. Interrupt Enable register (intEnable - address 0xFFE0 0FE4) bit description
The Interrupt Clear register (IntClear) is a Write Only register with an address of
0xFFE0 0FE8. The interrupt clear register bit definition is shown in
Table 230. Interrupt Clear register (IntClear - address 0xFFE0 0FE8) bit description
The interrupt clear register is write-only. Writing a 1 to a bit of the IntClear register clears
the corresponding bit in the status register. Writing a 0 will not affect the interrupt status.
The Interrupt Set register (IntSet) is a Write Only register with an address of
0xFFE0 0FEC. The interrupt set register bit definition is shown in
Bit
4
5
6
7
11:8
12
13
31:14
Bit
0
1
2
3
4
5
6
7
11:8
12
13
31:14
Symbol
TxUnderrunIntEn Enable for interrupt trigger on transmit buffer or descriptor
TxErrorIntEn
TxFinishedIntEn
TxDoneIntEn
-
SoftIntEn
WakeupIntEn
-
Symbol
RxOverrunIntClr
RxErrorIntClr
RxFinishedIntClr
RxDoneIntClr
TxUnderrunIntClr
TxErrorIntClr
TxFinishedIntClr
TxDoneIntClr
-
SoftIntClr
WakeupIntClr
-
Rev. 04 — 26 August 2009
Function
underrun situations.
Enable for interrupt triggered when all transmit descriptors
Enable for interrupt triggered when a descriptor has been
Enable for interrupt triggered by the SoftInt bit in the IntStatus
Enable for interrupt triggered by a Wakeup event detected by
Enable for interrupt trigger on transmit errors.
have been processed i.e. on the transition to the situation
where ProduceIndex == ConsumeIndex.
transmitted while the Interrupt bit in the Control field of the
descriptor was set.
Unused
register, caused by software writing a 1 to the SoftIntSet bit in
the IntSet register.
the receive filter.
Unused
Function
Writing a ’1’ to one of these bits clears (0 to 7) the
corresponding status bit in interrupt status register
IntStatus.
Unused
Writing a ’1’ to one of these bits (12 and/or 13) clears the
corresponding status bit in interrupt status register
IntStatus.
Unused
Chapter 11: LPC24XX Ethernet
Table
Table
UM10237
© NXP B.V. 2009. All rights reserved.
11–231.
11–230.
240 of 792
Reset
value
0
0
0
0
0
0
0
0
0x0
0
0
0x0
Reset
value
0
0
0
0
0x0
0
0
0x0
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