P89LV51RD2FA,512 NXP Semiconductors, P89LV51RD2FA,512 Datasheet - Page 45

• Manufacturer Part Number: P89LV51RD2FA,512
• Description: IC 80C51 MCU 1024 RAM 44PLCC
• Manufacturer: NXP Semiconductors
• Series: 89LVr

Specifications of P89LV51RD2FA,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: P89LV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Package: 44PLCC
• Device Core: 80C51
• Family Name: 89LV
• Maximum Speed: 40 MHz
• For Use With: 622-1017 - BOARD 44-ZIF PLCC SOCKET622-1008 - BOARD FOR LPC9103 10-HVSON
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 935274176512; P89LV51RD2FA; P89LV51RD2FA

NXP Semiconductors
P89LV51RB2_RC2_RD2_5
Product data sheet
Fig 18. SPI transfer format with CPHA = 1
Fig 19. Block diagram of programmable WDT
S PICL K (CPOL = 0)
S PICL K (CPOL = 1)
6.8 Watchdog timer
S PICL K cycle #
external reset
CLK (XTAL1)
(for reference)
(from master)
SS (to slave)
(from slave)
The device offers a programmable Watchdog Timer (WDT) for fail safe protection against
software deadlock and automatic recovery.
To protect the system against software deadlock, the user software must refresh the WDT
within a user-defined time period. If the software fails to do this periodical refresh, an
internal hardware reset will be initiated if enabled (WDRE = 1). The software can be
designed such that the WDT times out if the program does not work properly.
The WDT in the device uses the system clock (XTAL1) as its time base. So strictly
speaking, it is a Watchdog counter rather than a WDT. The WDT register will increment
every 344064 crystal clocks. The upper 8-bits of the time base register (WDTD) are used
as the reload register of the WDT.
The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User
software can clear WDTS by writing ‘1' to it.
Figure 19
WDT operation. During Idle mode, WDT operation is temporarily suspended, and
resumes upon an interrupt exit from idle.
The time-out period of the WDT is calculated as follows:
where WDTD is the value loaded into the WDTD register and f
frequency.
Period = (255
MOSI
MISO
WDTC
provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control
COUNTER
MSB
MSB
1
WDTD)
Rev. 05 — 15 December 2009
2
6
6
344064
clks
344064
3
5
5
UPPER BYTE
4
WDTD
WDT
4
4
1 / f
5
3
3
P89LV51RB2/RC2/RD2
CLK (XTAL1)
WDT reset
6
2
2
8-bit microcontrollers with 80C51 core
7
1
1
LSB
002aaa531
8
internal reset
LSB
osc
is the oscillator
002aaa530
© NXP B.V. 2009. All rights reserved.
45 of 76