P89LPC938FDH,529 NXP Semiconductors, P89LPC938FDH,529 Datasheet - Page 48

• Manufacturer Part Number: P89LPC938FDH,529
• Description: IC 80C51 MCU FLASH 8K 28-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC938FDH,529

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 28-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 26
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC9x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1014 - BOARD FOR LPC9XX TSSOP622-1011 - BOARD FOR LPC938 TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2013-5; 935278546529; P89LPC938FDH-S

Philips Semiconductors
9397 750 14051
Product data sheet
8.4.5 Dual channel, continuous conversion mode
8.4.6 Single step mode
8.5.1 Timer triggered start
8.5.2 Start immediately
8.5.3 Edge triggered
8.5 Conversion start modes
8.6 Boundary limits interrupt
after the remaining input channels have been converted. After all selected channels have
been converted, the process will repeat starting with the first selected channel. Additional
conversion results will again cycle through the eight result register pairs, overwriting the
previous results.Continous conversions continue until terminated by the user.
This is a variation of the auto scan continuous conversion mode where conversion occurs
on two user-selectable inputs. The result of the conversion of the first channel is placed in
the result register pair, AD0DAT0R and AD0DAT0L. The result of the conversion of the
second channel is placed in result register pair, AD0DAT1R and AD0DAT1L. The first
channel is again converted and its result stored in AD0DAT2R and AD0DAT2L. The
second channel is again converted and its result placed in AD0DAT3R and AD0DAT3L,
etc. An interrupt is generated, if enabled, after every set of four or eight conversions (user
selectable).
This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any
combination of the eight input channels can be selected for conversion. After each
channel is converted, an interrupt is generated, if enabled, and the A/D waits for the next
start condition. May be used with any of the start modes.
An A/D conversion is started by the overflow of Timer 0. Once a conversion has started,
additional Timer 0 triggers are ignored until the conversion has completed. The Timer
triggered start mode is available in all A/D operating modes.
Programming this mode immediately starts a conversion.This start mode is available in all
A/D operating modes.
An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has
started, additional edge triggers are ignored until the conversion has completed. The edge
triggered start mode is available in all A/D operating modes.
The A/D converter has both a high and low boundary limit register. The user may select
whether an interrupt is generated when the conversion result is within (or equal to) the
high and low boundary limits or when the conversion result is outside the boundary limits.
An interrupt will be generated, if enabled, if the result meets the selected interrupt criteria.
The boundary limit may be disabled by clearing the boundary limit interrupt enable.
An early detection mechanism exists when the interrupt criteria has been selected to be
outside the boundary limits. In this case, after the four MSBs have been converted, these
four bits are compared with the four MSBs of the boundary high and low registers. If the
four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits)
an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt
Rev. 01 — 25 February 2005
8-bit microcontroller with 10-bit A/D converter
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
P89LPC938
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