AT91SAM9XE512-CU Atmel, AT91SAM9XE512-CU Datasheet - Page 152

• Manufacturer Part Number: AT91SAM9XE512-CU
• Description: MCU ARM9 512K FLASH 217-BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE512-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 96
• Interface Type: EBI/Ethernet/SPI/TWI/USART/USB
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 6
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 180 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.3.3.5
152
AT91SAM9XE128/256/512 Preliminary
GPNVM Bit
One error can be detected in the EEFC_FSR register after a programming sequence:
It is possible to clear lock bits previously set. Then the locked region can be erased or pro-
grammed. The unlock sequence is:
One error can be detected in the EEFC_FSR register after a programming sequence:
The status of lock bits can be returned by the Enhanced Embedded Flash Controller (EEFC).
The Get Lock Bit status sequence is:
For example, if the third bit of the first word read in the EEFC_FRR is set, then the third lock
region is locked.
One error can be detected in the EEFC_FSR register after a programming sequence:
Note:
GPNVM bits do not interfere with the embedded Flash memory plane. Refer to the product defi-
nition section for information on the GPNVM Bit Action.
The set GPNVM bit sequence is:
• The Set Lock command (SLB) and a page number to be protected are written in the Flash
• When the locking completes, the bit FRDY in the Flash Programming Status Register
• If the lock bit number is greater than the total number of lock bits, then the command has no
• a Command Error: a bad keyword has been written in the EEFC_FCR register.
• The Clear Lock command (CLB) and a page number to be unprotected are written in the
• When the unlock completes, the bit FRDY in the Flash Programming Status Register
• If the lock bit number is greater than the total number of lock bits, then the command has no
• a Command Error: a bad keyword has been written in the EEFC_FCR register.
• The Get Lock Bit command (GLB) is written in the Flash Command Register. FARG field is
• When the command completes, the bit FRDY in the Flash Programming Status Register
• Lock bits can be read by the software application in the EEFC_FRR register. The first word
• a Command Error: a bad keyword has been written in the EEFC_FCR register.
• Start the Set GPNVM Bit command (SGPB) by writing the Flash Command Register with the
Command Register.
(EEFC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR,
the interrupt line of the System Controller is activated.
effect. The result of the SLB command can be checked running a GLB (Get Lock Bit)
command.
Flash Command Register.
(EEFC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR,
the interrupt line of the System Controller is activated.
effect.
meaningless.
(EEFC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR,
the interrupt line of the System Controller is activated.
read corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as
it is meaningful. Extra reads to the EEFC_FRR register return 0.
SGPB command and the number of the GPNVM bit to be set.
Access to the Flash in read is permitted when a set, clear or get lock bit command is performed.
6254C–ATARM–22-Jan-10