AT91SAM7X512-CU Atmel, AT91SAM7X512-CU Datasheet - Page 517

• Manufacturer Part Number: AT91SAM7X512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: CAN, SPI, SSC, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 100TFBGA
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 55MHz
• Total Internal Ram Size: 128KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

36.6.4.6
36.6.4.7
6120H–ATARM–17-Feb-09
Error Interrupt Handler
Overload
When one of the error counters values exceeds 96, an increased error rate is indicated to the
controller through the WARN bit in CAN_SR register, but the node remains error active. The cor-
responding interrupt is pending while the interrupt is set in the CAN_IMR register.
Refer to the Bosch CAN specification v2.0 for details on fault confinement.
WARN, BOFF, ERRA and ERRP (CAN_SR) represent the current status of the CAN bus and
are not latched. They reflect the current TEC and REC (CAN_ECR) values as described in
tion 36.6.4.5 “Fault Confinement” on page
Based on that, if these bits are used as an interrupt, the user can enter into an interrupt and not
see the corresponding status register if the TEC and REC counter have changed their state.
When entering Bus Off Mode, the only way to exit from this state is 128 occurrences of 11 con-
secutive recessive bits or a CAN controller reset.
In Error Active Mode, the user reads:
In Error Passive Mode, the user reads:
In Bus Off Mode, the user reads:
The CAN interrupt handler should do the following:
The overload frame is provided to request a delay of the next data or remote frame by the
receiver node (“Request overload frame”) or to signal certain error conditions (“Reactive over-
load frame”) related to the intermission field respectively.
Reactive overload frames are transmitted after detection of the following error conditions:
The CAN controller can generate a request overload frame automatically after each message
sent to one of the CAN controller mailboxes. This feature is enabled by setting the OVL bit in the
CAN_MR register.
• ERRA =1
• ERRP = 0
• BOFF = 0
• ERRA = 0
• ERRP =1
• BOFF = 0
• ERRA = 0
• ERRP =1
• BOFF =1
• Only enable one error mode interrupt at a time.
• Look at and check the REC and TEC values in the interrupt handler to determine the current
• Detection of a dominant bit during the first two bits of the intermission field
• Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant bit
state.
by a receiver or a transmitter at the last bit of an error or overload frame delimiter
AT91SAM7X512/256/128 Preliminary
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