AT91SAM7X512-CU Atmel, AT91SAM7X512-CU Datasheet - Page 160

• Manufacturer Part Number: AT91SAM7X512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: CAN, SPI, SSC, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 100TFBGA
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 55MHz
• Total Internal Ram Size: 128KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TFBGA
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

160
AT91SAM7X512/256/128 Preliminary
Note:
Note:
5. Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re-
6. The interrupt handler can then proceed as required, saving the registers that will be
7. The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that
8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indi-
assertion of the nIRQ to be taken into account by the core. This can happen if an inter-
rupt with a higher priority than the current interrupt occurs.
used and restoring them at the end. During this phase, an interrupt of higher priority
than the current level will restart the sequence from step 1.
the interrupt is completed in an orderly manner.
cate to the AIC that the current interrupt is finished. This causes the current level to be
popped from the stack, restoring the previous current level if one exists on the stack. If
another interrupt is pending, with lower or equal priority than the old current level but
with higher priority than the new current level, the nIRQ line is re-asserted, but the inter-
rupt sequence does not immediately start because the “I” bit is set in the core.
SPSR_irq is restored. Finally, the saved value of the link register is restored directly into
the PC. This has the effect of returning from the interrupt to whatever was being exe-
cuted before, and of loading the CPSR with the stored SPSR, masking or unmasking
the interrupts depending on the state saved in SPSR_irq.
If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared dur-
ing this phase.
The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of
masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored,
the mask instruction is completed (interrupt is masked).
6120H–ATARM–17-Feb-09