ATSAM3U1CA-CU Atmel, ATSAM3U1CA-CU Datasheet - Page 861

• Manufacturer Part Number: ATSAM3U1CA-CU
• Description: IC MCU 32BIT 64KB FLASH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U1CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 20 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

38. Pulse Width Modulation (PWM)
38.1
38.2
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Description
Embedded Characteristics
The PWM macrocell controls 4 channels independently. Each channel controls two complemen-
tary square output waveforms. Characteristics of the output waveforms such as period, duty-
cycle, polarity and dead-times (also called dead-bands or non-overlapping times) are configured
through the user interface. Each channel selects and uses one of the clocks provided by the
clock generator. The clock generator provides several clocks resulting from the division of the
PWM master clock (MCK).
All PWM macrocell accesses are made through registers mapped on the peripheral bus. All
channels integrate a double buffering system in order to prevent an unexpected output wave-
form while modifying the period, the duty-cycle or the dead-times.
Channels can be linked together as synchronous channels to be able to update their duty-cycle
or dead-times at the same time.
The update of duty-cycles of synchronous channels can be performed by the Peripheral DMA
Controller Channel (PDC) which offers buffer transfer without processor Intervention.
The PWM macrocell provides 8 independent comparison units capable of comparing a pro-
grammed value to the counter of the synchronous channels (counter of channel 0). These
comparisons are intended to generate software interrupts, to trigger pulses on the
dent event lines (in order to synchronize ADC conversions with a lot of flexibility independently of
the PWM outputs), and to trigger PDC transfer requests.
The PWM outputs can be overridden synchronously or asynchronously to their channel counter.
The PWM block provides a fault protection mechanism with 4 fault inputs
fault condition and to override the PWM outputs asynchronously.
For safety usage, some control registers are write-protected.
• 4 Channels
• Common Clock Generator Providing Thirteen Different Clocks
• Independent Channels
– A Modulo n Counter Providing Eleven Clocks
– Two Independent Linear Dividers Working on Modulo n Counter Outputs
– Independent 16-bit Counter for Each Channel
– Independent Complementary Outputs with 12-bit Dead-Time Generator (Also Called
– Independent Enable Disable Command for Each Channel
– Independent Clock Selection for Each Channel
– Independent Period, Duty-Cycle and Dead-Time for Each Channel
– Independent Double Buffering of Period, Duty-Cycle and Dead-Times for Each
– Independent Programmable Selection of The Output Waveform Polarity for Each
Dead-Band or Non-Overlapping Time) for Each Channel
Channel
Channel
SAM3U Series
SAM3U Series
, cap
able of detecting a
2
indepen-
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