ATSAM3U1CA-CU Atmel, ATSAM3U1CA-CU Datasheet - Page 655
ATSAM3U1CA-CU
Manufacturer Part Number
ATSAM3U1CA-CU
Description
IC MCU 32BIT 64KB FLASH 100TFBGA
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U1CA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
57
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b, 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
20 KB
Interface Type
3xUSART, TWI, 4xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
57
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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33.10.6
Name:
Addresses: 0x40084020 (0), 0x40088020 (1)
Access:
Reset:
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in
page 646
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in
RXRDY behavior in Slave mode can be seen in
page 646
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in
6430D–ATARM–25-Mar-11
TXBUFE
31
23
15
–
–
7
–
and
and
TWI Status Register
TWI_SR
Read-only
0x0000F009
Figure 33-31 on page
Figure 33-31 on page
RXBUFF
OVRE
30
22
14
–
–
6
ENDTX
GACC
646.
646.
29
21
13
–
–
5
Figure 33-8 on page
Figure 33-10 on page
Figure 33-26 on page
ENDRX
SVACC
Figure 33-28 on page
Figure 33-8 on page 627
28
20
12
–
–
4
EOSACC
SVREAD
27
19
11
–
–
3
627.
628.
642,
644,
and in
Figure 33-29 on page
Figure 33-29 on page
SCLWS
TXRDY
26
18
10
–
–
2
Figure 33-10 on page
SAM3U Series
ARBLST
RXRDY
25
17
–
–
9
1
645,
645,
628.
Figure 33-30 on
Figure 33-30 on
TXCOMP
NACK
24
16
–
–
8
0
655
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