ATSAM3U1CA-CU Atmel, ATSAM3U1CA-CU Datasheet - Page 151

• Manufacturer Part Number: ATSAM3U1CA-CU
• Description: IC MCU 32BIT 64KB FLASH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U1CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 20 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

13.16.4
13.16.4.1
13.16.4.2
13.16.4.3
13.16.4.4
6430D–ATARM–25-Mar-11
TBB and TBH
Syntax
Operation
Restrictions
Condition flags
Table Branch Byte and Table Branch Halfword.
where:
Rn
then the address of the table is the address of the byte immediately following the TBB or TBH
instruction.
Rm
LSL #1 doubles the value in Rm to form the right offset into the table.
These instructions cause a PC-relative forward branch using a table of single byte offsets for
TBB, or halfword offsets for TBH. Rn provides a pointer to the table, and Rm supplies an index
into the table. For TBB the branch offset is twice the unsigned value of the byte returned from
the table. and for TBH the branch offset is twice the unsigned value of the halfword returned
from the table. The branch occurs to the address at that offset from the address of the byte
immediately after the TBB or TBH instruction.
The restrictions are:
These instructions do not change the flags.
• Rn must not be SP
• Rm must not be SP and must not be PC
• when any of these instructions is used inside an IT block, it must be the last instruction of the
IT block.
TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
is the register containing the address of the table of branch lengths. If Rn is PC,
is the index register. This contains an index into the table. For halfword tables,
SAM3U Series
151