AT91SAM7X128B-AU Atmel, AT91SAM7X128B-AU Datasheet - Page 448
AT91SAM7X128B-AU
Manufacturer Part Number
AT91SAM7X128B-AU
Description
IC MCU 128KB FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7X128B-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
JTAG, SPI, UART
Maximum Clock Frequency
55 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
62
Ram Memory Size
32KB
Cpu Speed
55MHz
No. Of Timers
1
Rohs Compliant
Yes
Cpu Family
91S
Device Core
ARM7TDMI
Device Core Size
32b
Frequency (max)
55MHz
Total Internal Ram Size
32KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7X128B-AU
Manufacturer:
Atmel
Quantity:
1 929
Part Number:
AT91SAM7X128B-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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34.2
Figure 34-1. Block Diagram
448
MCK
UDPCK
udp_int
external_resume
Block Diagram
SAM7X512/256/128 Preliminary
Atmel Bridge
MCU
APB
Bus
to
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by
reading and writing 8-bit values to APB registers.
The UDP peripheral requires two clocks: one peripheral clock used by the MCK domain and a
48 MHz clock used by the 12 MHz domain.
A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).
The signal external_resume is optional. It allows the UDP peripheral to wake up once in system
mode. The host is then notified that the device asks for a resume. This optional feature must be
also negotiated with the host during the enumeration.
U
e
n
e
a
e
s
c
r
I
t
r
f
W
a
p
p
e
Master Clock
Domain
r
r
USB Device
RAM
FIFO
Dual
Port
Recovered 12 MHz
Domain
W
a
p
p
e
r
r
Suspend/Resume Logic
12 MHz
Interface
Engine
Serial
SIE
txoen
eopn
txd
rxdm
rxd
rxdp
6120I–ATARM–06-Apr-11
Transceiver
Embedded
USB
DM
DP
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