AT91SAM7X128B-AU Atmel, AT91SAM7X128B-AU Datasheet - Page 43
AT91SAM7X128B-AU
Manufacturer Part Number
AT91SAM7X128B-AU
Description
IC MCU 128KB FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7X128B-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
JTAG, SPI, UART
Maximum Clock Frequency
55 MHz
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7X-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
62
Ram Memory Size
32KB
Cpu Speed
55MHz
No. Of Timers
1
Rohs Compliant
Yes
Cpu Family
91S
Device Core
ARM7TDMI
Device Core Size
32b
Frequency (max)
55MHz
Total Internal Ram Size
32KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7X128B-AU
Manufacturer:
Atmel
Quantity:
1 929
Part Number:
AT91SAM7X128B-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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11.2.6
6120I–ATARM–06-Apr-11
Thumb Instruction Set Overview
Table 11-2.
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same
physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also
access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the
Mnemonic
MOV
ADD
SUB
RSB
CMP
TST
AND
EOR
MUL
SMULL
SMLAL
MSR
B
BX
LDR
LDRSH
LDRSB
LDRH
LDRB
LDRBT
LDRT
LDM
SWP
MCR
LDC
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store Multiple instructions
• Exception-generating instruction
ARM Instruction Mnemonic List
Operation
Move
Add
Subtract
Reverse Subtract
Compare
Test
Logical AND
Logical Exclusive OR
Multiply
Sign Long Multiply
Signed Long Multiply Accumulate
Move to Status Register
Branch and Exchange
Load Word
Load Signed Halfword
Load Signed Byte
Load Half Word
Load Byte
Load Register Byte with Translation
Load Register with Translation
Load Multiple
Swap Word
Move To Coprocessor
Load To Coprocessor
Branch
SAM7X512/256/128 Preliminary
Mnemonic
CDP
MVN
ADC
SBC
RSC
CMN
TEQ
BIC
ORR
MLA
UMULL
UMLAL
MRS
BL
SWI
STR
STRH
STRB
STRBT
STRT
STM
SWPB
MRC
STC
Operation
Coprocessor Data Processing
Move Not
Add with Carry
Subtract with Carry
Reverse Subtract with Carry
Compare Negated
Test Equivalence
Bit Clear
Logical (inclusive) OR
Multiply Accumulate
Unsigned Long Multiply
Unsigned Long Multiply Accumulate
Move From Status Register
Branch and Link
Software Interrupt
Store Word
Store Half Word
Store Byte
Store Register Byte with Translation
Store Register with Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
43
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