AT32UC3A1128-AUT Atmel, AT32UC3A1128-AUT Datasheet - Page 574
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AT32UC3A1128-AUT
Manufacturer Part Number
AT32UC3A1128-AUT
Description
IC MCU AVR32 128KB FLASH 100TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A1128-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Controller Family/series
AT32UC3A
No. Of I/o's
69
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Package
100TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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For isochronous, bulk and interrupt OUT endpoints:
This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.
• RXSTPI: Received SETUP Interrupt Flag
For control endpoints, set by hardware to signal that the current bank contains a new valid SETUP packet. This triggers an
EPXINT interrupt if RXSTPE = 1.
Shall be cleared by software (by setting the RXSTPIC bit) to acknowledge the interrupt and to free the bank.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means UNDERFI for isochronous IN/OUT
endpoints.
• UNDERFI: Underflow Interrupt Flag
For isochronous IN/OUT endpoints, set by hardware when an underflow error occurs. This triggers an EPXINT interrupt if
UNDERFE = 1.
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then auto-
matically sent by the USB controller.
An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU
is not fast enough. The packet is lost.
Shall be cleared by software (by setting the UNDERFIC bit) to acknowledge the interrupt.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means RXSTPI for control endpoints.
• NAKOUTI: NAKed OUT Interrupt Flag
Set by hardware when a NAK handshake has been sent in response to an OUT request from the host. This triggers an
EPXINT interrupt if NAKOUTE = 1.
Shall be cleared by software (by setting the NAKOUTIC bit) to acknowledge the interrupt.
• NAKINI: NAKed IN Interrupt Flag
Set by hardware when a NAK handshake has been sent in response to an IN request from the host. This triggers an EPX-
INT interrupt if NAKINE = 1.
Shall be cleared by software (by setting the NAKINIC bit) to acknowledge the interrupt.
• OVERFI: Overflow Interrupt Flag
Set by hardware when an overflow error occurs. This triggers an EPXINT interrupt if OVERFE = 1.
For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for
the packet. The packet is acknowledged and the Received OUT Data interrupt (RXOUTI) is raised as if no overflow had
occurred. The bank is filled with all the first bytes of the packet that fit in.
32058J–AVR32–04/11
Shall be cleared by software (by setting the RXOUTIC bit) to acknowledge the interrupt and to free the bank.
Set by hardware at the same time as FIFOCON when the current bank is full. This triggers an EPXINT interrupt if
RXOUTE = 1.
Shall be cleared by software (by setting the RXOUTIC bit) to acknowledge the interrupt, what has no effect on the
endpoint FIFO.
The software then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT endpoint is com-
posed of multiple banks, this also switches to the next bank. The RXOUTI and FIFOCON bits are updated by
hardware in accordance with the status of the next bank.
RXOUTI shall always be cleared before clearing FIFOCON.
AT32UC3A
574
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