AT32UC3A1128-AUT Atmel, AT32UC3A1128-AUT Datasheet - Page 314
AT32UC3A1128-AUT
Manufacturer Part Number
AT32UC3A1128-AUT
Description
IC MCU AVR32 128KB FLASH 100TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A1128-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Controller Family/series
AT32UC3A
No. Of I/o's
69
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Package
100TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 314 of 826
- Download datasheet (20Mb)
Figure 26-12. Asynchronous Start Detection
Figure 26-13. Asynchronous Character Reception
32058J–AVR32–04/11
Clock (x16)
Baud Rate
Sampling
Sampling
Sampling
Baud Rate
Example: 8-bit, Parity Enabled
Detection
Clock
RXD
RXD
Start
Clock
RXD
The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start
bit is detected and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data
bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8
(OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop
bit are sampled on each 8 sampling clock cycle.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits
as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization
mechanism only, the number of stop bits has no effect on the receiver as it considers only one
stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the
transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking
for a new start bit so that resynchronization can also be accomplished when the transmitter is
operating with one stop bit.
Figure 26-12 on page 314
reception when USART operates in asynchronous mode.
1
1
2
2
samples
3
3
16
4
4
D0
5
5
samples
16
6
6
D1
Detection
7
7
Rejection
samples
Start
Start
16
8
0
and
D2
1
1
samples
16
2
2
Figure 26-13 on page 314
3
3
D3
samples
4
4
16
5
D4
samples
6
16
7
D5
samples
8
16
9 10 11 12 13 14 15 16
D6
samples
16
illustrate start detection and character
D7
samples
16
Parity
Bit
samples
16
Stop
Bit
Sampling
AT32UC3A
D0
314
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