AT32UC3A1128-AUT Atmel, AT32UC3A1128-AUT Datasheet - Page 512
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AT32UC3A1128-AUT
Manufacturer Part Number
AT32UC3A1128-AUT
Description
IC MCU AVR32 128KB FLASH 100TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A1128-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Controller Family/series
AT32UC3A
No. Of I/o's
69
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Package
100TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 512 of 826
- Download datasheet (20Mb)
30.7.2.4
30.7.2.5
Figure 30-14. Endpoint Activation Algorithm
32058J–AVR32–04/11
Endpoint Reset
Endpoint Activation
An endpoint can be reset at any time by setting its EPRSTX bit in the UERST register. This is
recommended before using an endpoint upon hardware reset or when a USB bus reset has
been received. This resets:
Note that the interrupt sources located in the UESTAX register are not cleared when a USB bus
reset has been received.
The endpoint configuration remains active and the endpoint is still enabled.
The endpoint reset may be associated with a clear of the data toggle sequence as an answer to
the CLEAR_FEATURE USB request. This can be achieved by setting the RSTDT bit (by setting
the RSTDTS bit).
In the end, the firmware has to clear the EPRSTX bit to complete the reset operation and to start
using the FIFO.
The endpoint is maintained inactive and reset (see
details) as long as it is disabled (EPENX = 0). The Data Toggle Sequence bit-field (DTSEQ) is
also reset.
The algorithm represented on
As long as the endpoint is not correctly configured (CFGOK = 0), the controller does not
acknowledge the packets sent by the host to this endpoint.
The CFGOK bit is set by hardware only if the configured size and number of banks are correct
compared to their maximal allowed values for the endpoint (see
the maximal FIFO size (i.e. the DPRAM size).
•the internal state machine of this endpoint;
•the receive and transmit bank FIFO counters;
•all the registers of this endpoint (UECFGX, UESTAX, UECONX), except its configuration
(ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE) and its Data Toggle Sequence bit-field (DTSEQ).
Yes
EPENX = 1
CFGOK ==
Activation
UECFGX
Activated
Endpoint
Endpoint
EPTYPE
EPSIZE
ALLOC
EPDIR
EPBK
1?
No
ERROR
Figure 30-14
Enable the endpoint.
Configure the endpoint:
Allocate the configured DPRAM
banks.
Test if the endpoint configuration
is correct.
must be followed in order to activate an endpoint.
- type;
- direction;
- size;
- number of banks.
Section 30.7.2.4 on page 512
Table 30-1 on page
AT32UC3A
497) and to
for more
512
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