AT32UC3A1128-AUT Atmel, AT32UC3A1128-AUT Datasheet - Page 499
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AT32UC3A1128-AUT
Manufacturer Part Number
AT32UC3A1128-AUT
Description
IC MCU AVR32 128KB FLASH 100TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A1128-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Controller Family/series
AT32UC3A
No. Of I/o's
69
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Package
100TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 499 of 826
- Download datasheet (20Mb)
30.3
Figure 30-1. Block Diagram
32058J–AVR32–04/11
Block Diagram
Controller
Manager
Interrupt
Power
HSB
PB
USB GCLK @ 48 MHz
USB
The USB controller provides a hardware device to interface a USB link to a data flow stored in a
dual-port RAM (DPRAM).
The USB controller requires a 48 MHz ± 0.25% reference clock, which is the USB generic clock
generated from one of the power manager oscillators, optionally through one of the power man-
ager PLLs.
The 48 MHz clock is used to generate a 12 MHz full-speed (or 1.5 MHz low-speed) bit clock from
the received USB differential data and to transmit data according to full- or low-speed USB
device tolerance. Clock recovery is achieved by a digital phase-locked loop (a DPLL, not repre-
sented), which complies with the USB jitter specifications.
HSB MUX
Master
Slave
HSB0
HSB1
Slave Interface
User Interface
Local
DMA
HSB
USB Interrupts
32 bits
System Clock
Domain
Allocation
USB 2.0
DPRAM
Core
PEP
USB Clock
Domain
Controller
GPIO
AT32UC3A
VBUS
D-
D+
USB_ID
USB_VBOF
499
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