AT89C5132-RORUL Atmel, AT89C5132-RORUL Datasheet - Page 98

• Manufacturer Part Number: AT89C5132-RORUL
• Description: MCU 8051 FLASH USB 80TQFP
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5132-RORUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
• Peripherals: I²S, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

98
AT89C5132
Reset Value = 0000 0000b
Table 79. MMCON1 Register
MMCON1 (S:E5h) – MMC Control Register 1
Reset Value = 0000 0000b
Table 80. MMCON2 Register
Number
Number
BLEN3
7 - 4
Bit
Bit
6
5
4
3
2
1
0
7
3
2
1
0
Mnemonic Description
Mnemonic Description
MBLOCK
RESPEN
BLEN3:0
CRCDIS
DATDIR
CMDEN
CRPTR
DATEN
DTPTR
CTPTR
BLEN2
DFMT
RFMT
Bit
Bit
6
Data Transmit Pointer Reset Bit
Set to reset the write pointer of the data FIFO.
Clear to release the write pointer of the data FIFO.
Command Receive Pointer Reset Bit
Set to reset the read pointer of the receive command FIFO.
Clear to release the read pointer of the receive command FIFO.
Command Transmit Pointer Reset Bit
Set to reset the write pointer of the transmit command FIFO.
Clear to release the read pointer of the transmit command FIFO.
Multi-block Enable Bit
Set to select multi-block data format.
Clear to select single block data format.
Data Format Bit
Set to select the block-oriented data format.
Clear to select the stream data format.
Response Format Bit
Set to select the 48-bit response format.
Clear to select the 136-bit response format.
Clear to enable the CRC7 computation when receiving a response.
Block Length Bits
Refer to Table 77 for Bits description. Do not program value > 1011b.
Data Direction Bit
Set to select data transfer from host to card (write mode).
Clear to select data transfer from card to host (read mode).
Data Transmission Enable Bit
Set and clear to enable data transmission immediately or after response has
been received.
Response Enable Bit
Set and clear to enable the reception of a response following a command
transmission.
CRC7 Disable Bit
Set to disable the CRC7 computation when receiving a response.
Command Transmission Enable Bit
Set and clear to enable transmission of the command FIFO to the card.
BLEN1
5
BLEN0
4
DATDIR
3
DATEN
2
RESPEN
1
4173E–USB–09/07
CMDEN
0