AT89C5132-RORUL Atmel, AT89C5132-RORUL Datasheet - Page 15
![MCU 8051 FLASH USB 80TQFP](/photos/12/13/121358/313-80-tqfp_sml.jpg)
AT89C5132-RORUL
Manufacturer Part Number
AT89C5132-RORUL
Description
MCU 8051 FLASH USB 80TQFP
Manufacturer
Atmel
Series
AT89C513xr
Specifications of AT89C5132-RORUL
Core Processor
C52X2
Core Size
8-Bit
Speed
20MHz
Connectivity
IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
Peripherals
I²S, POR, WDT
Number Of I /o
44
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number
Manufacturer
Quantity
Price
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4173E–USB–09/07
CKCON (S:8Fh) – Clock Control Register
Reset Value = 0000 000Xb
Table 2. PLLNDIV Register
PLLNDIV (S:EEh) – PLL N Divider Register
Reset Value = 0000 0000b
Bit Number
Bit Number
TWIX2
6-0
7
7
6
5
4
3
2
1
0
7
7
-
Mnemonic
Mnemonic
TWIX2
WDX2
WDX2
T1X2
T0X2
SIX2
N6:0
Bit
X2
N6
Bit
6
6
-
-
-
Description
Two-Wire Clock Control Bit
Set to select the oscillator clock divided by 2 as TWI clock input (X2 independent).
Clear to select the peripheral clock as TWI clock input (X2 dependent).
Watchdog Clock Control Bit
Set to select the oscillator clock divided by 2 as watchdog clock input (X2 independent).
Clear to select the peripheral clock as watchdog clock input (X2 dependent).
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enhanced UART Clock (Mode 0 and 2) Control Bit
Set to select the oscillator clock divided by 2 as UART clock input (X2 independent).
Clear to select the peripheral clock as UART clock input (X2 dependent)..
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer 1 Clock Control Bit
Set to select the oscillator clock divided by two as Timer 1 clock input (X2 independent).
Clear to select the peripheral clock as Timer 1 clock input (X2 dependent).
Timer 0 Clock Control Bit
Set to select the oscillator clock divided by two as timer 0 clock input (X2 independent).
Clear to select the peripheral clock as timer 0 clock input (X2 dependent).
System Clock Control Bit
Clear to select 12 clock periods per machine cycle (STD mode, F
Set to select 6 clock periods per machine cycle (X2 mode, F
Description
Reserved
The value read from this bit is always 0. Do not set this bit.
PLL N Divider
7-bit N divider.
N5
5
5
-
SIX2
N4
4
4
N3
3
3
-
T1X2
N2
2
2
CPU
AT89C5132
T0X2
= F
N1
CPU
1
1
PER
= F
= F
PER
OSC
= F
).
N0
X2
0
0
OSC
/
2).
15
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