AT89C5132-RORUL Atmel, AT89C5132-RORUL Datasheet - Page 76

• Manufacturer Part Number: AT89C5132-RORUL
• Description: MCU 8051 FLASH USB 80TQFP
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5132-RORUL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
• Peripherals: I²S, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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AT89C5132
Reset Value = 0000 0000b
Table 62. UEPSTAX Register
UEPSTAX (Soh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM)
Number
6 - 4
1 - 0
DIR
Bit
7
3
2
7
Mnemonic Description
EPTYPE1:
EPDIR
EPEN
DTGL
Bit
0
-
6
-
Endpoint Enable Bit
Set to enable the endpoint according to the device configuration. Endpoint 0 shall
always be enabled after a hardware or USB bus reset and participate in the
device configuration.
Clear to disable the endpoint according to the device configuration.
Reserved
The values read from this bit is always 0. Do not set this bit.
Data Toggle Status Bit (Read-only)
Set by hardware when a DATA1 packet is received.
Cleared by hardware when a DATA0 packet is received.
Note: When a new data packet is received without DTGL toggling from 1 to 0 or 0
to 1, a packet may have been lost. When this occurs for a Bulk endpoint, the
device firmware shall consider the host has retried transmitting a properly
received packet because the host has not received a valid ACK, then the
firmware shall discard the new packet (N.B. The endpoint resets to DATA0 only
upon configuration).
For interrupt endpoints, data toggling is managed as for Bulk endpoints when
used.
For Control endpoints, each SETUP transaction starts with a DATA0 and data
toggling is then used as for Bulk endpoints until the end of the Data stage (for a
control write transfer); the Status stage completes the data transfer with a DATA1
(for a control read transfer).
For Isochronous endpoints, the device firmware shall retrieve every new data
packet and may ignore this bit.
Endpoint Direction Bit
Set to configure IN direction for Bulk, Interrupt and Isochronous endpoints.
Clear to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.
This bit has no effect for Control endpoints.
Endpoint Type Bits
Set this field according to the endpoint configuration (Endpoint 0 shall always be
configured as Control):
0
0
1
1
STALLRQ
0
1
0
1
5
Control endpoint
Isochronous endpoint
Bulk endpoint
Interrupt endpoint
TXRDY
4
STLCRC
3
RXSETUP
2
RXOUT
1
4173E–USB–09/07
TXCMP
0